Layer-Centric SNN Event Routing for Sparse Memory Efficiency
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Solution Overview
Problem
Existing neuron-centric event-routing methods for spiking neural networks (SNN) are inefficient in terms of memory usage and weight reuse, particularly in implementing sparse connections, which limits the depth of implemented SNNs and hinders efficient use of on-chip memory.
Innovation Solution
A layer-centric event-routing architecture (LaCERA) that optimizes data structure using a neuron address index method with global, layer-wise, and neuron-group indices, performs layer-wise event-routing using lookup tables, and compresses synaptic weight data to increase weight reuse.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If neuron-centric event-routing methods are used, then event routing can be performed using predefined addresses with lookup tables, but memory usage becomes inefficient particularly for sparse connections
Solution Approach 1:
The patent segments the event routing process into two distinct phases: an offline compilation phase that generates optimized routing tables, and an online inference phase that executes routing using compact data structures. This segmentation allows complex routing logic to be pre-computed, enabling efficient memory usage during actual neural network execution without sacrificing routing capability.
Solution Approach 2:
The patent performs preliminary action by pre-computing and storing optimized routing information in compact data structures during an offline compilation phase. The routing tables are generated in advance with optimized memory layouts that account for sparse connections, so that during online inference, memory access is minimized and efficient.
2Adaptability or versatility
If neuron-centric event-routing with lookup tables is used, then routing can be performed for all neuron connections, but weight reuse is limited and on-chip memory capacity is strictly limited
Solution Approach 1:
The patent implements dynamic memory allocation strategies where the routing data structures are adapted based on the specific network topology being executed. The compilation phase analyzes the actual connection patterns and generates optimized routing tables that allocate memory dynamically according to sparse or dense connection patterns, rather than using fixed neuron-centric allocations.
Solution Approach 2:
The patent changes the parameter representation from neuron-centric addresses to connection-pattern-based indices. By analyzing actual weight matrices and generating routing tables that reflect the true sparsity patterns of the network, the system optimizes memory usage parameters to match the actual computational requirements rather than theoretical maximums.
3Productivity
If general-purpose digital hardware such as CPU and GPU is used, then computation can be performed, but computational complexity scales with the number of time steps and wall clock time is lengthened
Solution Approach 1:
The patent replaces the sequential mechanical execution model of general-purpose processors with an event-driven asynchronous execution model optimized for neural network workloads. By using compact routing tables that enable direct memory access patterns and eliminate unnecessary sequential overhead, the system achieves parallel execution efficiency similar to specialized hardware while maintaining software flexibility.
4Device complexity
If neuron-centric event-routing is used, then routing can be performed using simple crossbar or LUT structures, but memory usage efficiency is poor for implementing layers with sparse connections
Solution Approach 1:
The patent segments the routing information into multiple hierarchical levels: network topology descriptors, layer-specific connection patterns, and neuron-level routing entries. This segmentation allows the system to store only relevant connection information at each level, eliminating the need to represent all possible neuron connections even in sparse networks.
Solution Approach 2:
The patent introduces a compilation dimension by separating offline table generation from online execution. The routing tables are constructed in an offline dimension where complex analysis can be performed, then compressed into compact formats for online execution, effectively adding a time dimension to the memory efficiency optimization.
Data Source
AI summary
Proposed are a neuromorphic processor structure for layer unit event routing of a spiking neural network, and a control method therefor. A layer unit event routing method of a spiking neural network, proposed in the present invention, comprises the steps of: optimizing a data structure for performing layer unit event routing by using a neuron address index method including a global index, a layer unit index, and a neuron group index; performing the layer unit event routing by using an LUT for each of the global index, the layer unit index, and the neuron group index; and compressing synapse weight data according to global address operations of the layer unit event routing for the neuron group index.