Layer-ID Detector for 3D-IC Using Voting Mechanism
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Solution Overview
Problem
Existing methods for identifying layer-ID in 3D-IC devices are costly and inefficient, especially as the number of stacked chips increases, as they require complex structures and additional electrodes, which complicate the selection process and increase costs.
Innovation Solution
A novel initiation type layer-ID detector for 3D stacked chip devices utilizing a random generator, a layer-ID designation (voting) mechanism circuit, and a counter to generate and output a layer-ID signal, employing a voting mechanism to determine the identification number of each layer through a series of AND gates and an operational amplifier.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional identification methods are used for layer-ID detection in 3D-IC devices, then identification can be achieved, but device complexity and manufacturing cost increase due to additional electrodes and complex structures
Solution Approach 1:
The patent combines the layer-ID detection function with the existing TSV structure by utilizing the TSV plug as part of the detection circuit. The TSV plug serves dual purposes: electrical connection between layers and as a component in the detection circuit, thereby eliminating the need for separate detection electrodes and reducing structural complexity
Solution Approach 2:
The detection circuit is designed to perform multiple functions: it can identify the layer-ID of individual chips and also determine the total number of stacked chips. This multi-functional approach eliminates the need for separate detection mechanisms, reducing overall device complexity while maintaining identification accuracy
2Measurement precision
If traditional identification methods are used for layer-ID detection in 3D-IC devices, then identification can be achieved, but manufacturing cost increases due to additional electrodes and complex structures
Solution Approach 1:
The patent merges the detection function with existing TSV structures, eliminating the need for additional dedicated detection electrodes. By reusing the TSV plug and existing pad structures for detection purposes, the manufacturing process is simplified and material costs are reduced while maintaining identification accuracy
3Quantity of substance
If the number of stacked chips increases, then storage capacity increases, but identification complexity and cost increase proportionally
Solution Approach 1:
The detection circuit automatically identifies layer-IDs and determines the total number of chips through self-service mechanisms. Each chip's detection result is automatically registered and used to update the total chip count, eliminating the need for external intervention or complex control systems even as the number of stacked chips increases
Solution Approach 2:
The detection circuit incorporates feedback mechanisms where the output of each detection stage is fed back to update the system state. The counter circuit receives feedback from each layer's detection result and automatically updates the total chip count, enabling scalable identification without increasing complexity proportionally
Data Source
AI summary
A layer-ID detector for multilayer 3D-IC, including a random generator to generate a random signal, a layer-ID designation mechanism circuit coupled to the random generator to generate a layer-ID designating signal, and a counter coupled to the layer-ID designating signal to output a layer-ID signal.