Extensible Layer Mapping for In-Design Parasitic Extraction
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Solution Overview
Problem
The increasing complexity of integrated circuit (IC) designs makes it challenging to accurately analyze parasitic electrical effects during the design process, as existing methods require a completed design for parasitic checks, leading to long turn-around-times and the need for in-design parasitic verification.
Innovation Solution
A general extensible layer mapping approach that maps design database layers to process layers directly, enabling in-design parasitic checks by converting in-design layers to derived layers using layer derivation rules and generating a one-to-one mapping for parasitic extraction tools.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If parasitic checks are performed only after design completion, then manufacturing precision is improved, but loss of time increases
Solution Approach 1:
The patent applies preliminary action by enabling parasitic extraction and analysis during the design phase rather than waiting for design completion. The layer mapping system allows parasitic checks to be performed on incomplete designs by mapping available design layers to process layers, extracting parasitic data early, and providing feedback to designers before the design is finalized, thus reducing turn-around-time while maintaining analysis accuracy.
2Adaptability or versatility
If design complexity increases, then functionality improves, but difficulty of detecting and measuring worsens
Solution Approach 1:
The patent introduces an intermediary layer mapping system that bridges design database layers and process layers. This intermediary mapping layer simplifies the detection and measurement of parasitic effects in complex designs by providing a standardized interface between the complex design structure and the parasitic extraction tool, making parasitic analysis manageable even as design complexity increases.
Solution Approach 2:
The patent applies segmentation by dividing the layer mapping process into distinct sections: a first section with derivation rules for converting design layers to process layers, and a second section with one-to-one mapping relationships. This segmentation allows the parasitic extraction tool to handle complex designs by processing different layer mapping aspects separately, reducing the difficulty of detecting and measuring parasitic effects in complex designs.
Data Source
AI summary
Techniques and systems for implementing a general extensible layer mapping approach that maps between integrated circuit (IC) design database layers and process layers are described. A first IC design layout having in-design layers can be converted into a second IC design layout having derived layers, wherein said converting comprises mapping the in-design layers to the derived layers by applying a set of layer derivation rules to shapes in the IC design layout, and wherein the set of layer derivation rules implements a one-to-many mapping between the in-design layers and the derived layers. Next, a one-to-one mapping between the derived layers and process layers used in a parasitic extraction tool can be generated. Parasitic extraction on the IC design layout then be performed by providing the second IC design layout and the one-to-one mapping to the parasitic extraction tool.