Layer Performance Metric for IC Placement and Routing
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Solution Overview
Problem
Existing IC design tools face challenges in predicting design success due to varying interconnect widths and wiring pitches, leading to poor quality and long convergence times in meeting power, area, and timing constraints.
Innovation Solution
The use of a Layer Performance Metric (LPM) to compute a ratio of wire length to delay for timing paths, enabling accurate placement, routing, and optimization by assigning metal layers based on LPM values, which are maintained throughout the design flow, and using these assignments to calculate timing and routing feasibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If existing IC design tools are used with varying interconnect widths and wiring pitches, then the design can be implemented with different metal layer characteristics, but the design success prediction becomes difficult and convergence time increases
Solution Approach 1:
The patent introduces a Layer Performance Metric (LPM) that quantifies the electrical performance of different metal layers by computing the ratio of wire length to delay. This parameter transformation allows the design tools to accurately predict timing behavior across varying interconnect widths and wiring pitches, enabling convergence within iterative design flows while maintaining adaptability to different metal layer characteristics.
Solution Approach 2:
The patent replaces traditional empirical or rule-based layer assignment methods with a physics-based LPM calculation system. By substituting the mechanical/heuristic approach with a quantitative metric derived from actual wire length and delay measurements, the system achieves more accurate timing prediction and faster convergence without sacrificing adaptability to varying interconnect characteristics.
2Device complexity
If traditional placement and routing methods are used without LPM, then the design flow is simpler, but the predicted design success is poor and quality is reduced
Solution Approach 1:
The patent performs LPM calculation and metal layer assignment during the placement stage, before routing begins. This preliminary action establishes an accurate performance model early in the design flow, enabling reliable success prediction and guiding subsequent routing decisions. The LPM values computed at placement are maintained throughout the design flow, providing consistent timing predictions without significantly increasing overall complexity.
3Ease of operation
If metal layers are not assigned based on LPM, then routing has more flexibility, but routing congestion increases and timing constraints are harder to meet
Solution Approach 1:
The patent assigns specific metal layers to nets based on their individual LPM values and timing requirements. Instead of applying a uniform layer assignment strategy, the system evaluates each net's performance characteristics and assigns layers locally optimized for that net's timing needs. This local quality approach maintains routing flexibility while ensuring timing constraints are met, as each net routes on layers that provide the appropriate performance characteristics.
Data Source
AI summary
Techniques and systems for using a layer performance metric (LPM) during integrated circuit (IC) design are described. Some embodiments can compute an LPM value for at least one timing path in the IC design, wherein the LPM value is equal to a ratio between a wire length of the timing path and a delay of the timing path. Next, the embodiments can use the LPM value of the timing path to perform at least one of placement, routing, or optimization of the timing path.