Layer-Specific Source Line Control for Stacked Memory Programming Disturb

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Solution Overview

Problem

In stacked memory array architectures, programming disturb occurs due to rate offsets between layers, leading to errors during sense operations as memory cell threshold voltages are increased from originally programmed levels.

Innovation Solution

Implementing a sense offset on a per-layer basis by adjusting sense conditions, such as shifting the target voltage range, using higher sense currents, precharging bit lines to higher voltages, and employing shorter bit line discharge times for slower programming layers relative to faster ones, to compensate for programming rate differences.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a common source line is shared by all layers, then device complexity is reduced, but programming disturb occurs due to rate offsets between layers

Engineering Contradiction:

Improvesource line architectureVSAvoidsense operation accuracy

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The common source line is segmented into layer-specific source lines, with each source line dedicated to a specific layer. This segmentation allows independent voltage control for each layer, enabling compensation for programming rate offsets without increasing overall system complexity significantly.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different voltage levels are applied to different source lines based on the specific programming characteristics of each layer. Slower programming layers receive higher source line voltages during programming to match the programming rate of faster layers, while during sense operations, appropriate source lines are selected based on the target layer.

Inventive Principle:

Principle #3Local quality

2Productivity

If higher programming voltages are applied to slower layers, then programming rate uniformity is improved, but programming stress is increased on faster layers

Engineering Contradiction:

Improveprogramming rate uniformityVSAvoidprogramming stress

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

The source line voltage is made dynamic and adjustable based on the programming phase and target layer. During programming, slower layers receive elevated source line voltages to accelerate their programming rate. During sense operations, the source line voltage is adjusted to appropriate levels for the specific layer being sensed, preventing unnecessary stress on other layers.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

Different voltage regimes are applied periodically based on the operation type. Programming operations use elevated voltages on specific source lines to accelerate programming, while sense operations use lower, layer-appropriate voltages. This periodic switching between voltage regimes allows rate uniformity during programming while minimizing stress during sense operations.

Inventive Principle:

Principle #19Periodic action

3Measurement precision

If per-layer sense offsets are implemented, then sense operation accuracy is improved, but device complexity increases

Engineering Contradiction:

Improvesense operation accuracyVSAvoidsense control architecture

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The sense offset is implemented by changing the source line voltage parameter for each layer based on its programming characteristics. During sense operations, the appropriate source line is selected and its voltage is adjusted according to the programming rate of the target layer. This parameter-based approach achieves per-layer sense offsets without requiring complex additional circuitry.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS9564227B2Memory device having a different source line coupled to each of a plurality of layers of memory cell arrays

Publication Date: 2017.02.07 MICRON TECHNOLOGY INC

AI summary

A sensing voltage may be applied to a particular memory cell that is in a particular layer of a plurality of layers of memory cells. While the sensing voltage is applied to the particular memory cell, a source voltage may be applied to an end of a string of memory cells that includes the particular memory cell. The source line voltage may be based on a programming rate of the particular layer.