Semiconductor Layer Stack Stress Balancing for Wafer Bow Control
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Solution Overview
Problem
As semiconductor devices shrink, achieving uniformity and minimizing roughness in deposited layers becomes increasingly challenging due to the stress caused by different materials, leading to wafer bow and decreased device performance and reliability.
Innovation Solution
A method of forming a stack of semiconductor layers by depositing silicon oxide, silicon, and silicon nitride layers using LPCVD or PECVD, with a stress layer deposited on the backside of the substrate to counteract the tensile or compressive stresses, managing stress through helium flowrate and RF power calibration to achieve target stress levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple layers of different semiconductor materials are deposited, then device functionality is improved, but wafer bow and stress increase
Solution Approach 1:
A stress layer is deposited on the backside of the substrate before depositing the frontside layers. This preliminary stress layer creates counteracting stress that compensates for the stress generated by subsequent frontside layers, preventing wafer bow and maintaining substrate flatness throughout the multi-layer deposition process.
Solution Approach 2:
The stress management approach transitions from single-sided (frontside only) to dual-sided deposition. By depositing a stress layer on the backside of the substrate and functional layers on the frontside, the solution utilizes both surfaces of the substrate to achieve stress balance, effectively adding a spatial dimension to stress management.
2Manufacturing precision
If deposition is performed to achieve uniformity, then layer quality is improved, but process complexity increases
Solution Approach 1:
Stress calibration is performed in advance by depositing test layers and measuring the resulting wafer bow. The measured stress values are used to determine the appropriate thickness and material composition of the backside stress layer. This preliminary calibration eliminates the need for complex real-time stress monitoring and adjustment during production, simplifying the overall process while maintaining high uniformity standards.
Solution Approach 2:
The stress layer thickness and material properties are determined based on feedback from wafer bow measurements taken after depositing reference layers. This feedback loop allows for precise control of stress compensation parameters, ensuring optimal layer uniformity without requiring overly complex deposition processes.
3Stability of the object's composition
If stress layer is deposited on backside, then wafer bow is reduced, but manufacturing steps increase
Solution Approach 1:
The deposition of the backside stress layer and frontside functional layers are merged into a single processing sequence without requiring separate equipment or process interruptions. The substrate is flipped once between stress layer deposition and functional layer deposition, combining multiple stress management functions into an integrated workflow that minimizes additional manufacturing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces wafer bow, improves uniformity, and enhances surface roughness, resulting in better adhesion and reduced substrate deviation, with standard deviation in uniformity less than 3% and roughness better than 1 nm RMS.
Implementation Method 1
depositing a first silicon nitride layer on the first silicon layer. Depositing the first silicon nitride layer includes flowing a gas that includes helium and silane or disilane through a plasma to form plasma effluents. The plasma is sustained with an RF power.
Implementation Method 2
flowing a gas that includes helium and silane or disilane through a plasma to form plasma effluents. The plasma is sustained with an RF power.
Implementation Method 3
depositing a stress layer on a side of the substrate opposite a side of the substrate with the first silicon oxide layer
Data Source
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AI summary
Embodiments of the present technology may include a method of forming a stack of semiconductor layers. The method may include depositing a first silicon oxide layer on a substrate. The method may also include depositing a first silicon layer on the first silicon oxide layer. The method may further include depositing a first silicon nitride layer on the first silicon layer. Depositing the first silicon nitride layer or a stress layer may include reducing stress in at least one of the first silicon layer, the first silicon oxide layer, or the substrate. In addition, the method may include depositing a second silicon layer on the first silicon nitride layer. The operations may form the stack of semiconductor layers, where the stack includes the first silicon oxide layer, the first silicon layer, the first silicon nitride layer, and the second silicon layer.