Layer Stack Trench Geometry for Low-Resistance Super Vias
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Solution Overview
Problem
Current semiconductor technologies face high resistivity issues in metallic connections within layer stacks, leading to undesirable voltage drops and potential shorts, which are exacerbated by certain geometries of vias and interconnects.
Innovation Solution
The method involves forming deep and narrow trenches in layer stacks, selectively etching to expose metal contacts, depositing barrier layers, and filling with conductive materials to reduce resistance and voltage drops, while also modifying feature shapes and depths to counteract higher resistivity materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional via and interconnect geometries are used, then manufacturing is simpler, but resistance and voltage drops increase undesirably
Solution Approach 1:
The via structure is segmented into multiple sections: a first section with a first diameter and a second section with a second diameter. This segmentation allows different geometric configurations in different regions of the via, optimizing electrical performance by reducing resistance and voltage drops while maintaining manufacturability through standardized processing steps.
Solution Approach 2:
Different sections of the via are given different local geometries - the first section has a larger diameter to reduce resistance at the interface with the transistor, while the second section has a smaller diameter to maintain spacing requirements. This local quality variation optimizes the overall electrical performance without requiring complete redesign of the entire via structure.
2Reliability
If via diameter is increased to reduce resistance, then electrical performance improves, but spacing between adjacent vias decreases
Solution Approach 1:
The via is divided into sections with different diameters, allowing the first section to have a larger diameter for reduced resistance while the second section maintains a smaller diameter to preserve spacing. This segmentation resolves the contradiction by applying different diameter requirements to different spatial locations within the same via structure.
Solution Approach 2:
The via geometry is extended into the vertical dimension with varying diameters at different depths. Instead of using a single large diameter throughout (which would reduce spacing), the via uses a tapered or multi-section geometry where the diameter changes with depth, allowing large cross-sectional area for low resistance while maintaining horizontal spacing between adjacent vias.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces resistance and voltage drops by up to 50% and simultaneously decreases the time constant of the layer stack, achieving desirable low-voltage connections and improved performance.
Implementation Method 1
selectively etching a deep trench disposed in the layer stack to form the modified deep trench
Implementation Method 2
depositing a barrier layer in the modified deep trench
Implementation Method 3
depositing a conductive filler material in the modified deep trench
Data Source
AI summary
Embodiments provided herein generally relate to methods of modifying portions of layer stacks. The methods include forming deep trenches and narrow trenches, such that a desirably low voltage drop between layers is achieved. A method of forming a deep trench includes etching portions of a flowable dielectric, such that a deep metal contact is disposed below the deep trench. The deep trench is selectively etched to form a modified deep trench. A method of forming a super via includes forming a super via trench through a second layer stack of a layer superstack. The methods disclosed herein allow for decreasing the resistance, and thus the voltage drop, of features in a semiconductor layer stack.