Semiconductor Device Layer Stacking for Miniature Transistors
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high integration, high-speed operation, and high reliability, particularly in applications requiring high-definition displays for virtual and augmented reality, with a need for transistors of minute sizes and improved on-state current.
Innovation Solution
A semiconductor device design incorporating a first and second transistor structure with specific layer configurations, including conductive and insulating layers, and semiconductor layers, optimized for minute size and high on-state current, utilizing metal oxide semiconductor layers and varying film densities and nitrogen content in insulating layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is reduced to achieve high integration, then integration degree is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from planar transistor structure to a three-dimensional structure with vertical stacking of multiple layers (conductive layers, insulating layers, and semiconductor layers). This dimensional change allows multiple transistor components to occupy the same footprint area vertically, achieving high integration without proportionally increasing manufacturing precision requirements in the planar direction.
Solution Approach 2:
The patent implements a nested structure where conductive layers, insulating layers, and semiconductor layers are stacked one on top of another in a vertical arrangement. Each layer is positioned within the boundaries of the layers below it, creating a compact nested configuration that maximizes integration density while maintaining manageable manufacturing precision at each individual layer interface.
2Area of stationary object
If transistor size is reduced to achieve high integration, then device area is reduced, but on-state current decreases
Solution Approach 1:
The patent compensates for the reduced on-state current from area reduction by utilizing vertical stacking to increase the effective channel area in the thickness direction. Multiple semiconductor layers stacked vertically provide cumulative conductive paths, maintaining high on-state current despite the reduced planar footprint area.
Solution Approach 2:
The patent employs composite material structures combining different semiconductor materials (such as silicon and silicon carbide) and insulating materials with specific dielectric properties. This allows optimization of each layer's contribution to current flow, maintaining high on-state current while achieving miniaturization through the composite structure's superior electrical characteristics.
3Power
If complex transistor structures are used to improve performance, then on-state current increases, but device complexity increases
Solution Approach 1:
The patent organizes the complex transistor structure into a systematic vertical stacking arrangement where conductive layers, insulating layers, and semiconductor layers are arranged in repeating patterns. This dimensional organization simplifies the manufacturing process by allowing each layer to be deposited and patterned independently using standard semiconductor fabrication techniques, reducing the overall complexity despite the multi-layer configuration.
Solution Approach 2:
The patent designs the transistor structure with universal interface designs where each layer serves multiple functions: conductive layers provide both current flow paths and alignment references for subsequent layers, insulating layers provide both electrical isolation and planarization surfaces. This multi-functionality reduces the total number of separate components and simplifies the overall device architecture despite the complex internal structure.
Data Source
AI summary
A semiconductor device (10) including a transistor having a minute size is provided. The semiconductor device includes a first transistor (100) and a second transistor (200). The first transistor includes a first conductive layer (112a), a first insulating layer (110) over the first conductive layer, a second insulating layer (120) over the first insulating layer, a second conductive layer (112b) over the second insulating layer, a first semiconductor layer (108), a third insulating layer (106), and a third conductive layer (104). The first insulating layer, the second insulating layer, and the second conductive layer have an opening reaching the first conductive layer. The first semiconductor layer is in contact with a top surface and a side surface of the second conductive layer, a side surface of the first insulating layer, the second insulating layer, and atop surface of the first conductive layer. The third insulating layer is provided over the first semiconductor layer. The third conductive layer is provided over the third insulating layer. The second transistor includes a second oxide semiconductor layer (208) over the second insulating layer, the third insulating layer over the second semiconductor layer, and a fourth conductive layer (204) including a region overlapping with the second semiconductor layer with the third insulating layer therebetween.