Layer-Transferred Semiconductor Structure With Trap-Rich Handle Wafer

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

High resistivity substrates in SOI technology are susceptible to parasitic surface conduction, leading to signal degradation and cross-talk in RF communication circuits, especially due to the formation of channel-like layers that affect the capacitance and linearity of signals, which existing trap rich layers formed before active layer processing are prone to degradation during high-temperature processing.

Innovation Solution

A layer transferred structure with a trap rich layer introduced after active layer processing, where the substrate is moved further away from the active layer, and a thicker bonding layer is used to reduce parasitic pathways and nonlinear capacitance, with the trap rich layer formed using techniques such as ion implantation or radiation to achieve high trap density without thermal degradation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a trap rich layer is formed before active layer processing, then parasitic surface conduction is reduced, but the trap rich layer is degraded by high-temperature processing steps

Engineering Contradiction:
Improveparasitic surface conduction reductionVSAvoidtrap rich layer integrity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The trap rich layer is formed in the handle wafer before bonding to the active layer, preparing the substrate to suppress parasitic conduction pathways in advance. This preliminary formation allows the trap rich layer to be positioned optimally without being exposed to degrading high-temperature processing steps that would occur if formed after active layer fabrication.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The semiconductor structure is divided into separate components: the active layer with device circuitry and the handle wafer with the trap rich layer. This segmentation allows each component to be processed independently under appropriate conditions, with the trap rich layer formed in the handle wafer away from the high-temperature processing zones affecting the active layer devices.

Inventive Principle:
Principle #1Segmentation

2Loss of energy

If the trap rich layer is positioned close to the active layer, then substrate loss is reduced, but manufacturing defects increase due to degradation during processing

Engineering Contradiction:
Improvesubstrate lossVSAvoidmanufacturing defects
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The handle wafer serves as an intermediary substrate that carries the trap rich layer. By bonding the active layer to the handle wafer, the trap rich layer is positioned close enough to the active layer to effectively suppress substrate loss and parasitic conduction, while the handle wafer protects the trap rich layer from direct exposure to manufacturing defects and degradation during subsequent processing steps.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively inhibits parasitic surface conduction and enhances RF performance by maintaining the integrity of the trap rich layer, reducing substrate loss, and minimizing manufacturing defects, thereby improving signal purity and reducing cross-talk in RF communication circuits.

Implementation Method 1

the trap rich layer formed using techniques such as ion implantation or radiation to achieve high trap density without thermal degradation

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Implementation Method 2

the trap rich layer formed using techniques such as ion implantation or radiation to achieve high trap density without thermal degradation

Methodology Applied
Scientific EffectRadiation: Radiation

Data Source

PatentUS9783414B2Forming semiconductor structure with device layers and TRL
Publication Date: 2017.10.10 QUALCOMM INC
  • US9783414B2 patent drawing
  • US9783414B2 patent drawing
  • US9783414B2 patent drawing

AI summary

A semiconductor wafer is formed with a first device layer having active devices. A handle wafer having a trap rich layer is bonded to a top surface of the semiconductor wafer. A second device layer having a MEMS device or acoustic filter device is formed on a bottom surface of the semiconductor wafer. The second device layer is formed either by monolithic fabrication processes or layer-transfer processes.