Layered Interconnection Bridge for Low-Inductance Power Modules
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Solution Overview
Problem
The design of power semiconductor modules using wide-band-gap semiconductors faces challenges due to increased switching speeds, which result in stronger oscillations and higher power losses, especially when many switches are connected in parallel with varying connection path lengths.
Innovation Solution
The implementation of an interconnection bridge with a layer structure comprising a first and second conductive layer separated by an insulating layer, which reduces gate control loop inductance by increasing inductive coupling, thereby improving switching behavior and reducing oscillations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If wide-band-gap semiconductors are used to achieve fast switching behavior, then switching speed is improved, but oscillations and power losses increase due to stronger electromagnetic interference
Solution Approach 1:
The patent transitions from planar interconnection to a three-dimensional stacked substrate architecture. Multiple substrates are arranged vertically with conductive layers extending between them, creating a layered structure that reduces current loop area and inductance while maintaining electrical connectivity
Solution Approach 2:
The patent implements nested conductive paths where control signal traces are positioned directly above or below power signal traces in adjacent substrate layers. This nesting arrangement creates tightly coupled differential pairs that cancel electromagnetic interference and reduce oscillations
2Power
If many wide-band-gap semiconductor devices are connected in parallel to achieve targeted current rating, then current capacity is improved, but connection path length variations increase causing synchronization issues
Solution Approach 1:
The patent creates equipotential connection regions on each substrate where multiple semiconductor devices connect to common conductive pads. This ensures that all devices in parallel experience identical electrical conditions and switching timing, eliminating synchronization issues caused by path length variations
Solution Approach 2:
The patent divides the parallel-connected devices into groups, with each group connected to a dedicated substrate. Control signals are distributed to each substrate independently, allowing for modular scaling of current capacity while maintaining uniform connection characteristics within each segment
3Ease of manufacture
If conventional interconnection methods are used for substrate connections, then manufacturing simplicity is maintained, but gate control loop inductance is too high affecting switching performance
Solution Approach 1:
The patent introduces intermediate conductive layers that extend vertically between stacked substrates. These intermediate conductors act as mediators that provide direct low-inductance pathways for control signals, eliminating the need for long lateral connections while maintaining manufacturing feasibility through standard layering processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution achieves a substantial reduction in gate inductance, leading to improved synchronization of switching behavior, reduced oscillations, and lower power losses during switching, while also allowing for the potential omission or reduction of gate resistors.
Implementation Method 1
reduces gate control loop inductance by increasing inductive coupling
Data Source
AI summary
A power semiconductor module includes a plurality of semiconductor switches arranged in a plurality of groups. Each semiconductor switch has a first terminal and a second terminal having a controlled path therebetween and a control terminal. A plurality of first group contacts are each connected to the first terminals of the semiconductor switches of a respective group and a plurality of second group contacts are each connected to the second terminals of the semiconductor switches of the respective group. A plurality of control group contacts are each connected to the control terminals of the semiconductor switches of the respective group. An interconnection bridge connects the control group contacts and the first group contacts of the plurality of groups. The interconnection bridge has a layer structure with a first conductive layer and a second conductive layer being separated by an insulating layer.