Layered Capacitor Electrodes in High-Resolution Display Devices

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Solution Overview

Problem

Display devices face limitations in achieving high resolution due to the restricted size of the display area, necessitating a reduction in pixel size without compromising performance.

Innovation Solution

The display device incorporates a capacitor structure where the first, second, and third capacitor electrodes overlap each other, allowing for a reduced pixel area by sharing electrodes, and utilizes oxide semiconductors and multiple transistors to enhance resolution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the number of pixels is increased to achieve high resolution, then the resolution is improved, but the area of each pixel must be reduced which complicates the device structure

Engineering Contradiction:
ImproveresolutionVSAvoidpixel structure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent merges multiple capacitor electrodes into a shared structure. Specifically, the first capacitor electrode and second capacitor electrode are formed as overlapping conductive layers, and the third capacitor electrode shares the same structure as the second semiconductor layer. This merging reduces the number of separate components and simplifies the overall pixel structure while maintaining high resolution capability

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The second capacitor electrode and third capacitor electrode serve multiple functions simultaneously. The second capacitor electrode acts as both the second electrode of the first capacitor and the first electrode of the second capacitor. Similarly, the third capacitor electrode (second semiconductor layer) serves as both the second electrode of the second capacitor and the semiconductor layer for transistor operation. This multi-functionality reduces structural complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Quantity of substance

If the pixel area is reduced to increase pixel density, then the resolution is improved, but maintaining electrical functionality becomes more difficult

Engineering Contradiction:
Improvepixel densityVSAvoidelectrical functionality
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent transitions from planar capacitor electrode arrangements to a three-dimensional overlapping structure. The capacitor electrodes are arranged in multiple layers with vertical overlap, creating capacitance through spatial separation in the z-dimension rather than requiring large lateral areas. This dimensional change enables high pixel density while maintaining sufficient capacitance values for reliable electrical functionality

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The capacitor electrodes are nested within each other in a layered structure. The first capacitor electrode is disposed on the first conductive layer, the second capacitor electrode is disposed on the first conductive layer and overlaps the first capacitor electrode, and the third capacitor electrode is formed in the second semiconductor layer. This nested arrangement maximizes the use of vertical space within the pixel area, enabling high pixel density while maintaining electrical functionality through proper capacitive coupling

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS12389681B2Display device and method of manufacturing the same
Publication Date: 2025.08.12 SAMSUNG DISPLAY CO LTD
  • US12389681B2 patent drawing
  • US12389681B2 patent drawing
  • US12389681B2 patent drawing

AI summary

A display device includes a first semiconductor layer, a first conductive layer disposed on the first semiconductor layer and including a first capacitor electrode at least partially overlapping the first semiconductor layer in a plan view to constitute a first transistor, a second capacitor electrode disposed on the first conductive layer and overlapping the first capacitor electrode in a plan view to constitute a first capacitor, a second semiconductor layer disposed on the second capacitor electrode and including a third capacitor electrode overlapping the second capacitor electrode in a plan view to constitute a second capacitor, a second conductive layer disposed on the second semiconductor layer and at least partially overlapping the second semiconductor layer, and a third conductive layer disposed over the second conductive layer to implement a high-resolution image by overlapping the first capacitor electrode, the second capacitor electrode, and the third capacitor electrode.