Layered Chip Packaging Structure for Mechanical Stress Distribution

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Solution Overview

Problem

Existing semiconductor packaging structures fail to optimally manage mechanical stresses and enhance the overall performance and reliability of semiconductor devices.

Innovation Solution

A chip packaging structure with multiple layers of varying strengths and moduli, including a compound layer, a first layer with higher strength and modulus, and subsequent layers with progressively lower strengths and moduli, arranged to distribute mechanical stresses effectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single-layer packaging structure is used, then the device complexity is low, but the stress management and reliability are insufficient

Engineering Contradiction:
Improvepackaging reliabilityVSAvoidpackaging structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The packaging structure is divided into multiple functional layers including a first packaging layer with first strength and first modulus, a second packaging layer with second strength and second modulus, and a third packaging layer with third strength and third modulus. Each layer serves specific stress management functions, with strengths and moduli relationships designed to optimize mechanical performance and reliability under various operating conditions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs composite packaging materials with different mechanical properties arranged in specific layers. The first packaging layer has higher strength and modulus than the second layer, which in turn has higher properties than the third layer. This composite structure allows the packaging to withstand different types of mechanical stresses while maintaining overall reliability.

Inventive Principle:
Principle #40Composite materials

2Strength

If high strength materials are used throughout the packaging structure, then the strength is high, but the stress distribution is uneven and reliability decreases

Engineering Contradiction:
Improvepackaging strengthVSAvoidstress distribution uniformity
Core Design Contradiction:
StrengthVSReliability

Solution Approach 1:

Different regions of the packaging structure have different mechanical properties tailored to local stress requirements. The first packaging layer (closest to the chip) has high strength and modulus to support the chip, the second layer has intermediate properties for stress transition, and the third layer has lower properties for flexible stress distribution. This gradient structure ensures optimal stress management across the entire packaging assembly.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent systematically varies the strength and modulus parameters across different packaging layers. The strength decreases from the first layer to the third layer, while the modulus follows a similar gradient. This parameter optimization creates a progressive stress distribution that enhances both overall strength and stress uniformity, resolving the contradiction between these two requirements.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If the first layer has larger surface area than the second layer, then the stress distribution is improved, but the manufacturing precision requirements increase

Engineering Contradiction:
Improvestress distributionVSAvoidlayer alignment precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The packaging structure is segmented into distinct layers with defined surface area relationships. The first layer has a larger surface area than the second layer, creating an overlapping configuration that improves stress distribution. This segmentation allows each layer to be manufactured and positioned independently while maintaining the desired stress management characteristics.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20260068753A1Chip packaging structure and method for forming the same
Publication Date: 2026.03.05 YANGTZE MEMORY TECH CO LTD
  • US20260068753A1 patent drawing
  • US20260068753A1 patent drawing
  • US20260068753A1 patent drawing

AI summary

A chip packaging structure and fabrication method are provided. The chip packaging structure includes: one or more dies stacked on a packaging substrate in a vertical direction; and a packaging body surrounding the one or more dies. The packaging body includes: a compound layer in direct contact with the one or more dies, where the compound layer includes a material having a reference strength and a reference modulus; a first layer adjacent to a top surface of the packaging body, where the first layer includes a material having a first strength and a first modulus, and the first strength being greater than the reference strength; and a second layer positioned between the first layer and the one or more dies along the vertical direction, where the second layer includes a material having a second strength and a second modulus, and the second modulus being less than the reference modulus.