Layered Data Block Rotation Circuit for Tight Timing Constraints
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Solution Overview
Problem
High-performance processing devices face challenges in meeting timing requirements for rotating data blocks of varying sizes, particularly in applications like machine learning, while also needing to minimize area cost and power consumption.
Innovation Solution
A logic circuit is designed with a layered multiplexer architecture that decomposes rotation operations across multiple levels, using smaller multiplexers and shared hardware resources to handle blocks of different sizes efficiently, ensuring timely processing and reduced resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single large multiplexer array is used to rotate data blocks, then the rotation operation can be completed in one step, but the area cost and power consumption increase significantly
Solution Approach 1:
The patent divides the data block into multiple segments and uses separate multiplexer arrays to process each segment in parallel. For example, an 8-byte block is divided into two 4-byte segments, each handled by a dedicated multiplexer array. This segmentation reduces the size of individual multiplexer arrays while maintaining overall rotation performance through parallel processing.
Solution Approach 2:
The patent introduces a layered processing dimension by organizing multiplexer arrays in hierarchical levels. First-layer arrays process individual byte segments, while second-layer arrays combine results to produce the final rotated block. This multi-dimensional approach transforms a single large operation into coordinated smaller operations across different processing levels.
2Productivity
If a single large multiplexer array is used to rotate data blocks, then the rotation operation can be completed in one step, but the timing requirements cannot be met in high-performance devices with short clock periods
Solution Approach 1:
By segmenting the rotation operation across multiple multiplexer arrays processing different byte segments in parallel, the critical path delay is reduced. Each multiplexer array handles a smaller subset of bytes, allowing the operation to complete within the short clock period of high-performance devices.
Solution Approach 2:
The patent performs preliminary rotation of individual byte segments through dedicated multiplexer arrays before combining the results. This preliminary processing of smaller units enables the overall operation to meet tight timing constraints that would be impossible with a single large multiplexer array.
3Area of stationary object
If smaller multiplexer arrays are used to reduce area cost, then the area cost and power consumption are minimized, but multiple layers and arrays are required to handle the rotation
Solution Approach 1:
The patent segments both the data block and the processing structure into matching smaller units. Each segment is handled by a dedicated multiplexer array, creating a systematic organization where the number of arrays and their size are directly related to the block size. This segmentation strategy reduces area while managing complexity through regular, predictable structure.
Solution Approach 2:
The patent designs multiplexer arrays that can handle multiple byte positions and rotation amounts through control signal manipulation. The same array structure serves universal purposes by selectively routing different input bytes to different output positions based on control inputs, reducing the need for dedicated hardware for each specific rotation case.
4Use of energy by stationary object
If smaller multiplexer arrays are used to minimize power consumption, then power consumption is reduced, but multiple layers and arrays are required to handle the rotation
Solution Approach 1:
By dividing the rotation operation across multiple smaller multiplexer arrays processing segments in parallel, the patent reduces the power consumption of individual arrays while maintaining overall performance. The segmented approach allows for more efficient power utilization distributed across multiple smaller processing units.
Data Source
AI summary
An execution unit performs a byte-wise rotation of an input data block. An input data array receives an input data block. Two first layer multiplexer arrays each receive a first layer data block comprising a respective subset of bytes of the input data block and a first layer control signal, and rotate the first layer data block by an amount indicated by the first layer control signal. The second layer multiplexer array receives a second control signal and selects between a corresponding byte of the first and second rotated first layer data blocks based on the second control signal. The execution unit also includes a control signal generator, configured to generate the first layer control signal and second layer control signal based on a received computer program instruction. Results of smaller block rotations are thus used as partial results for larger block rotation, avoiding large multiplexer arrays with complex wiring.