Layered Gate Structure for Lower DRAM Leakage and Resistance
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Solution Overview
Problem
The increasing integration of memory cells in semiconductor devices, such as DRAM, leads to manufacturing challenges including narrow process windows and increased leakage due to close component distances, necessitating improved methods to reduce gate-induced drain leakage current and word line resistance.
Innovation Solution
A semiconductor device structure is developed with a gate structure comprising a bottom lining layer, a bottom low work function material layer, and a conductive material layer, utilizing materials like titanium nitride and polycrystalline silicon, along with a method involving deposition and etching processes to form a residual lining layer and barrier layer, enhancing electrical isolation and reducing leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more memory cells are integrated to increase storage capability, then storage capability is improved, but manufacturing complexity increases and process window narrows
Solution Approach 1:
The gate structure is segmented into multiple functional layers: a bottom lining layer (silicon oxide) for isolation, a bottom low work function material layer for electrical control, and a top conductive material layer for signal transmission. This segmentation allows each layer to be optimized independently for its specific function, enabling high integration while maintaining manufacturability
Solution Approach 2:
The gate structure employs composite materials with different properties stacked together: silicon oxide (insulator) at the bottom, polycrystalline silicon or amorphous silicon (semiconductor with low work function) in the middle, and titanium nitride (conductive material) at the top. This composite structure resolves the contradiction by combining materials that individually address different aspects of the manufacturing challenge
2Speed
If pitch between semiconductor structures is shortened to improve performance, then performance is improved, but leakage increases due to close distances
Solution Approach 1:
The bottom lining layer of silicon oxide acts as an intermediary barrier between adjacent semiconductor structures. This insulating layer prevents direct electrical interaction and leakage between closely spaced structures, enabling pitch shortening while maintaining electrical isolation
Solution Approach 2:
The low work function material is selectively placed at the bottom of the gate structure where it provides localized electrical control, while the conductive material layer on top provides localized signal transmission. This local quality differentiation allows performance improvement through better control without increasing leakage
3Ease of manufacture
If gate structure is simplified to reduce manufacturing complexity, then ease of manufacture is improved, but ability to reduce leakage and resistance deteriorates
Solution Approach 1:
The bottom lining layer of silicon oxide is formed first as a preliminary isolation structure before depositing the low work function material and conductive material. This preliminary action establishes the isolation framework early in the process, simplifying subsequent steps while ensuring leakage prevention is built into the structure from the beginning
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure effectively reduces gate-induced drain leakage current and word line resistance, improving the process yield and performance of semiconductor devices.
Implementation Method 1
a bottom low work function material layer formed in the bottom lining layer
Implementation Method 2
a bottom conductive material layer formed in the bottom low work function material layer
Data Source
AI summary
A semiconductor device includes a substrate, an active region and a gate structure. The active region is located in the substrate and the gate structure is located in the active region. The gate structure includes a bottom lining layer, a bottom low work function material layer formed in the bottom lining layer, and a bottom conductive material layer formed in the bottom low work function material layer. In addition, a method of forming the semiconductor device is also disclosed.