Layered Imaging Element Chip for Endoscope Noise Reduction
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Solution Overview
Problem
Current endoscope imaging systems face limitations in improving image quality due to pixel rate constraints when transmitting analog imaging signals, making it difficult to increase the number of pixels without compromising image quality.
Innovation Solution
The system incorporates a layered configuration of chips, including a pixel chip, a transmission chip, and capacitative chips, with connecting portions that overlap orthogonally to reduce chip area and prevent noise, allowing for efficient digital signal transmission and downsizing of the imaging element.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of pixels of the imaging element is increased to improve image quality, then image quality should be improved, but the pixel rate limit of analog signal transmission via cable prevents further improvement
Solution Approach 1:
The patent replaces the analog signal transmission system with a digital signal transmission system. By incorporating an A/D conversion circuit on the imaging element to convert analog imaging signals to digital imaging signals, and using a digital signal transmission cable instead of analog cable, the system overcomes the pixel rate limitation of analog transmission and enables higher pixel rates for improved image quality
Solution Approach 2:
The patent transitions from two-dimensional chip layout to three-dimensional layered structure. Multiple chips (imaging element chip, A/D conversion chip, digital signal processing chip) are arranged in layers and connected via through-silicon vias (TSVs), enabling complex functionality while maintaining compact form factor and supporting higher pixel rates
2Adaptability or versatility
If multiple chips are layered and connected to integrate A/D conversion and digital signal processing, then functionality is improved, but chip area and device complexity increase
Solution Approach 1:
The patent implements a nested three-dimensional integrated structure where multiple functional chips are stacked and interconnected through through-silicon vias. The imaging element chip, A/D conversion chip, and digital signal processing chip are arranged in layers, with each chip containing its functional circuits and connections to other chips via TSVs, achieving high integration in a compact volume
Solution Approach 2:
The patent transitions from two-dimensional chip layout to three-dimensional layered structure. Multiple chips (imaging element chip, A/D conversion chip, digital signal processing chip) are arranged in layers and connected via through-silicon vias (TSVs), enabling complex functionality while maintaining compact form factor
3Area of stationary object
If connecting portions are arranged to overlap orthogonally to reduce chip area, then chip area is reduced, but noise interference may increase
Solution Approach 1:
The patent introduces ground layers and insulating films as intermediary elements between signal transmission lines in overlapping connecting portions. These intermediary layers shield the signal lines from electromagnetic interference and crosstalk, reducing noise while enabling compact three-dimensional interconnections through through-silicon vias
Solution Approach 2:
The patent applies different structural characteristics to different regions of the chip. In areas where connecting portions overlap, additional ground layers and insulating structures are provided to reduce noise, while other areas maintain simpler structures for signal transmission
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances image quality by enabling higher pixel densities while maintaining compact size, reducing noise interference, and allowing for effective image inspection during manufacturing without increasing chip size.
Implementation Method 1
plural capacitative chips, each capacitative chip having capacitance functioning as a bypass condenser for a power source in the power source unit
Data Source
AI summary
An imaging element includes: a pixel chip where a pixel unit and a vertical selecting unit are arranged, the pixel unit including plural pixels that are arranged in a two-dimensional matrix, the pixels being configured to generate and output imaging signals; a transmission chip where at least a power source unit and a transmission unit are arranged; plural capacitative chips, each capacitative chip having capacitance functioning as a bypass condenser for a power source in the power source unit; and plural connecting portions configured to electrically connect the pixel chip, the transmission chip, and the capacitative chip respectively to another chip. The transmission chip is layered and connected at a back surface side of the pixel chip. The capacitative chips are layered and connected at a back surface side of the transmission chip. The connecting portions are arranged so as to overlap one another.