Layered LDPC Decoder Architecture With Fewer Hardware Buffers
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Solution Overview
Problem
Conventional layered decoding architectures for LDPC codes require significant hardware area and suffer from low hardware utilization due to the need for large buffers, which impact convergence speed and efficiency.
Innovation Solution
A novel layered decoding architecture with reduced buffers, featuring a variable-to-check message magnitude memory, APP calculation unit, APP sign routing network, and check-node processor, which updates APP values using both check-to-variable and variable-to-check messages, eliminating the need for redundant buffers and improving hardware utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional layered decoding architecture stores APP values in large buffers, then decoding convergence speed is maintained, but hardware area increases and hardware utilization decreases
Solution Approach 1:
The patent extracts and eliminates redundant buffer storage requirements by implementing a streamlined architecture that computes and updates APP values on-the-fly during decoding operations, removing the need for large dedicated buffer memory while maintaining convergence performance
Solution Approach 2:
The patent implements dynamic computation of APP values during the decoding process, allowing the system to maintain current decoding state information without requiring static large-capacity buffers, thereby improving hardware utilization while preserving convergence speed
2Reliability
If conventional layered decoding architecture uses large buffers for message storage, then decoding accuracy is maintained, but hardware utilization decreases
Solution Approach 1:
The patent performs preliminary computation and preparation of message values before they are needed in subsequent decoding stages, allowing smaller buffers to suffice while maintaining the accuracy required for reliable LDPC decoding
Solution Approach 2:
The patent implements a mechanism where intermediate message values are computed, used immediately for decoding operations, and then discarded, with new values continuously regenerated as needed, eliminating the need for persistent large-buffer storage while preserving decoding accuracy
3Reliability
If conventional layered decoding architecture implements full APP value storage and updating, then decoding completeness is ensured, but device complexity increases
Solution Approach 1:
The patent segments the decoding architecture into functional modules that process and update APP values in a structured manner, ensuring decoding completeness through systematic coverage of all necessary computations while managing complexity through modular organization
Data Source
AI summary
A layered decoding architecture with a reduced number of hardware buffers for low-density parity-check (LDPC) decoding by storing a variable-to-check message. When a check node begins a new operation, a variable-to-check message (Q) is added to a check-to-variable message (R) obtained in previous check-node operation to obtain an updated APP value. Then, the R value for the check node in the layer being processed is deducted from the APP value to obtain a variable-to-check message (Q). This variable-to-check message is stored in the memory and inserted into the check node equation to obtain a check-to-variable message. Finally the check-to-variable message obtained in this operation is stored to the check-to-variable message shift register to complete the updating operation for the check node and the variable node for the layer being processed. Improved hardware utilization and fewer buffers, thus achieving a smaller hardware area while retaining the converge speed, is obtained.