Layered LDPC Decoder for Flash Memory Read Reliability
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Solution Overview
Problem
Non-volatile flash memory devices face challenges in accurately reading data due to overlapping threshold voltage distributions, leading to increased error rates as the number of bits programmed in each memory cell increases, causing reliability issues and read failures.
Innovation Solution
A semiconductor memory system employing a low-density parity-check (LDPC) decoder that includes a variable node selecting device, a variable node updating device, and a check node updating device, which sequentially select and update sub-matrices and nodes based on channel and check node messages to decode data accurately.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of bits programmed in each memory cell increases to achieve higher integration, then storage capacity is improved, but read reliability deteriorates due to overlapping threshold voltage distributions
Solution Approach 1:
The parity check matrix is divided into multiple sub-matrices arranged in a layered structure. The decoding process segments the computation into layer-by-layer processing, where each layer processes a subset of variable nodes and check nodes. This segmentation allows the decoder to handle the increased complexity from higher-bit storage by breaking down the error correction task into manageable stages, thereby maintaining read reliability despite increased storage capacity.
2Quantity of substance
If multi-bit cells are used to increase storage capacity, then integration is improved, but error rate increases due to threshold voltage distribution overlap
Solution Approach 1:
The LDPC decoder implements iterative feedback processing where check node messages are computed based on variable node messages, and these check node messages are fed back to update variable node messages in subsequent iterations. This feedback mechanism allows the decoder to progressively refine error corrections across multiple passes, effectively reducing the error rate generated by multi-bit cell threshold voltage overlaps while preserving the high storage capacity benefits.
3Reliability
If LDPC decoding is performed to reduce error rates, then read reliability is improved, but decoding complexity increases
Solution Approach 1:
The parity check matrix is organized into sub-matrices that form multiple layers. The decoder processes these layers sequentially, with each layer handling a specific subset of the decoding computations. This segmentation of the decoding process into layered stages reduces the instantaneous computational complexity compared to processing the entire matrix at once, while still achieving the full error correction capability needed for high read reliability.
Data Source
AI summary
A semiconductor memory system includes: a semiconductor memory device for storing a code word; a decoder for decoding stored the code word based on a parity check matrix formed of sub-matrices to generate decoded data; and a channel for coupling the semiconductor memory device to the decoder and providing the decoder with the stored code word, wherein the decoder includes: a variable node selecting device for sequentially selecting sub-matrices sharing the same layer of the parity check matrix and sequentially selecting variable nodes respectively corresponding to columns forming the selected sub-matrices; a variable node updating device for updating the selected variable nodes based on a channel message and check node messages provided to the selected variable nodes; and a check node updating device for updating the check nodes based on variable node messages provided to the check nodes coupled to the selected variable nodes.