Layered LDPC Decoder Architecture for High-Throughput Decoding
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Solution Overview
Problem
Current communication systems employing LDPC codes face challenges in achieving low bit error rates at high data rates due to latency constraints associated with traditional concatenated codes, limiting their application in high-speed communication systems.
Innovation Solution
The development of a novel LDPC decoder architecture that utilizes cyclic shifted identity sub-matrices and permuted identity sub-matrices, enabling accelerated decoding performance through layered or accumulating decoding methods, which can be pipelined to increase throughput and reduce hardware footprint while maintaining minimal coding gain loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional concatenated codes are used, then error correction capability is maintained, but latency increases and throughput decreases
Solution Approach 1:
The LDPC code is divided into multiple subcodes, each corresponding to a submatrix in the parity check matrix. Each subcode can be decoded independently or in parallel, breaking down the large decoding problem into smaller manageable units that reduce overall latency and enable parallel processing for higher throughput.
Solution Approach 2:
The patent introduces a layered decoding structure where decoding proceeds through multiple layers or stages. This adds a temporal dimension to the decoding process, allowing intermediate results to be accumulated and processed in subsequent layers, thereby reducing the number of iterations needed and improving throughput without sacrificing error correction capability.
2Reliability
If more decoding iterations are performed, then coding gain increases, but hardware complexity and area increase
Solution Approach 1:
By segmenting the LDPC code into subcodes with smaller parity check matrices, each subcode requires fewer iterations to converge. This segmentation allows the system to achieve the same overall coding gain with fewer total iterations, reducing the hardware resources needed for each decoding operation.
Solution Approach 2:
The patent employs preliminary processing steps such as syndrome calculation and subcode identification before the main decoding iterations. This preliminary action prepares the data in a format that enables more efficient iterative decoding, reducing the computational burden and hardware complexity required for achieving high coding gain.
3Productivity
If high data rates are implemented, then throughput increases, but latency constraints are violated
Solution Approach 1:
Segmenting the decoding process into parallel subcode decoders allows the system to maintain high data rates by processing multiple subcodes simultaneously. This parallelism increases effective throughput while keeping the latency for each individual subcode decoding within acceptable bounds.
Solution Approach 2:
The patent implements a periodic or iterative decoding structure where multiple passes are made through the decoding process. This periodic action allows the system to accumulate decoding results over time, achieving high throughput by distributing the computational load across multiple time periods while maintaining low per-iteration latency.
Data Source
AI summary
Accumulating LDPC (Low Density Parity Check) decoder. The accumulating decoding architecture described herein is applicable to LDPC codes operating on a parity check matrix, H, consisting of CSI (Cyclic Shifted Identity) sub-matrices (or matrix sub-blocks) or permuted identity sub-matrices (or matrix sub-blocks). In such a structure, the entire LDPC matrix is broken into square sub-matrices such that each sub-matrix consists of either a CSI sub-matrix or a permuted identity sub-matrix, or a null matrix. The iterative decoding process operates by updating of APP (a posteriori probability) or gamma (γ) values and check edge message (λ) values, and this by updating one or more individual rows within a number of sub-matrix rows (or all sub-matrix or sub-block rows) are processed in parallel. The amount of parallelism is specified by the designer and is typically an integer divisor of the sub-matrix (or sub-block) size.