Layered LDPC Decoding With Partial Reliability Updates
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Solution Overview
Problem
Existing error correction techniques for low-density parity-check (LDPC) codes face challenges in balancing powerful error correction with constraints such as latency, throughput, and power consumption, particularly in portable electronic devices.
Innovation Solution
The implementation of an error correction circuit with variable nodes and check nodes, where variable nodes are implemented as circulant memories and check nodes as XOR circuits, using a layered approach to update reliability data based on parity data from check nodes, reducing memory usage and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional LDPC error correction techniques are used, then error correction capability is improved, but memory usage and decoder logic complexity increase
Solution Approach 1:
The LDPC code is divided into multiple layers, where each layer corresponds to a subset of check nodes. The decoding process iterates through layers sequentially, updating variable node values based on parity checks from each layer. This segmentation reduces the complexity of individual decoding steps while maintaining overall error correction capability through multiple iterations.
Solution Approach 2:
The decoding process employs periodic iteration through the layered structure, repeatedly cycling through all layers until convergence or maximum iterations are reached. Each iteration performs systematic updates of variable node reliability values based on accumulated parity check results from previous iterations, enabling progressive error correction with controlled complexity.
2Reliability
If traditional LDPC error correction techniques are used, then error correction capability is improved, but power consumption increases
Solution Approach 1:
By segmenting the decoding process into layered iterations, the patent enables early termination when errors are corrected within fewer iterations. This reduces the average power consumption compared to traditional methods that must complete all iterations regardless of convergence, while maintaining strong error correction capability through the structured layered approach.
Solution Approach 2:
The layered decoding structure allows the system to perform partial decoding operations when fewer iterations suffice for error correction. The patent executes only the necessary number of iterations required to achieve convergence, avoiding unnecessary computational cycles and associated power consumption while still achieving the required error correction performance.
3Reliability
If traditional LDPC error correction techniques are used, then error correction capability is improved, but latency increases
Solution Approach 1:
The layered structure segments the decoding process into independent stages that can be processed sequentially with predictable timing. Each layer processes a subset of check nodes, allowing for optimized pipeline execution and reducing the critical path delay compared to traditional approaches that must process all check nodes in each iteration, thereby reducing overall decoding latency.
Data Source
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Figure 2A~2C
Figure 2D~2F
AI summary
The present disclosure includes apparatuses and methods related to updating reliability data. A number of methods can include receiving, at a variable node, either a first reliability data value with a first hard data value or a second reliability data value with a second hard data value, sending the first hard data value or the second hard data value to each check node coupled to the variable node according to a parity check code, and updating the reliability data based on input from less than all of the check nodes.