Layered LDPC Decoder with Instant Syndrome Convergence Detection
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Solution Overview
Problem
Conventional layered LDPC decoders are sub-optimal in determining convergence and decoding efficiency due to the need for multiple iterations and excessive use of resources, as they consider all layers before declaring convergence, which can waste time and power.
Innovation Solution
The introduction of physical syndrome memories allows for instant syndrome computation, enabling the decoder to signal successful decoding without additional iterations by storing syndrome values and using intelligent LDPC code design to restrict non-zero circulants, facilitating simultaneous access to syndrome memories and reducing the number of required memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional layered LDPC decoders process all layers before declaring convergence, then decoding reliability is improved, but decoding time and power consumption increase
Solution Approach 1:
The patent introduces a convergence detection mechanism that performs preliminary checks during the decoding process to detect convergence before all layers are completely processed. This allows the decoder to stop early when convergence is detected, reducing decoding time while maintaining reliability through the preliminary convergence verification.
Solution Approach 2:
The patent implements a feedback mechanism where the convergence detection unit continuously monitors decoding progress and provides feedback to control whether additional layers are processed. This feedback loop enables dynamic termination of the decoding process based on actual convergence status, preventing unnecessary processing time and power consumption.
2Reliability
If conventional layered LDPC decoders process all layers before declaring convergence, then decoding accuracy is improved, but power consumption increases
Solution Approach 1:
The convergence detection mechanism performs preliminary verification during the decoding process to determine when convergence has been achieved. This allows the system to stop processing layers early when convergence is detected, significantly reducing power consumption while maintaining decoding accuracy through the preliminary convergence check.
Solution Approach 2:
The feedback mechanism from the convergence detection unit continuously monitors decoding accuracy and provides control signals to terminate processing when convergence is achieved. This prevents unnecessary power consumption from processing additional layers beyond what is needed for accurate decoding.
3Measurement precision
If syndrome values are computed and stored for all layers, then convergence detection accuracy is improved, but memory resource usage increases
Solution Approach 1:
The patent extracts and stores only the essential syndrome values needed for convergence detection in dedicated syndrome storage units, rather than storing all syndrome values from all layers. This selective extraction approach maintains convergence detection accuracy while significantly reducing memory resource usage.
Solution Approach 2:
The patent segments the syndrome storage into specific syndrome storage units that store only the relevant syndrome values required for convergence detection. This segmentation allows precise convergence detection while minimizing memory resource consumption by storing only necessary data.
Data Source
AI summary
Apparatuses and methods associated with instant syndrome computation in a layered LDPC decoder are described. According to one embodiment, an apparatus includes a plurality of hardware layers, where a hardware layer is configured to compute a syndrome value from one or more bit values in the codeword. The apparatus includes a plurality of physical memories configured to store a plurality of syndrome values, where a physical memory is configured to store syndrome values computed by one or more hardware layers. The apparatus includes circuitry configured to simultaneously store a syndrome value computed by a hardware layer in physical memories associated with a bit in the codeword. The apparatus includes a decode logic configured to signal successful decoding of the codeword based, at least in part, on determining that a set of syndromes are satisfied based on values stored in the plurality of physical memories.