Layered Memory Error Correction for Uncorrectable Bit Errors
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Solution Overview
Problem
Memory devices face challenges in correcting uncorrectable errors detected by single error correcting and dual error detecting (SECDED) procedures, leading to undesirable latencies and reliability issues when errors occur, such as double-bit errors.
Innovation Solution
Implementing a layered error detection approach by using a second error detection procedure, like a cyclic redundancy check (CRC), on a broader set of bits that includes the initially detected erroneous bits and additional bits, to generate candidate sets and identify error-free alternatives, thereby correcting errors without resorting to reset procedures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If SECDED procedure is used for error detection, then error detection capability is improved, but error correction capability deteriorates for uncorrectable errors
Solution Approach 1:
The patent divides error correction into multiple stages: first using SECDED for single-bit error correction, then using CRC-based candidate generation for multi-bit error correction. This segmentation allows each stage to handle specific error types efficiently, resolving the contradiction between detection precision and correction capability.
Solution Approach 2:
The patent introduces CRC (cyclic redundancy check) as an intermediary mechanism between SECDED detection and final error correction. The CRC enables generation of candidate corrected values for uncorrectable errors, serving as a bridge that extends correction capability beyond what SECDED alone can achieve.
2Reliability
If reset procedure is performed for uncorrectable errors, then system reliability is improved, but latency increases
Solution Approach 1:
The patent performs preliminary error detection using SECDED and generates candidate corrected values using CRC before actually needing to correct errors. This preliminary preparation allows rapid error correction when errors are detected, avoiding the need for time-consuming reset procedures and reducing overall latency.
Solution Approach 2:
The patent implements a feedback mechanism where CRC results are used to validate candidate corrected values. This feedback loop enables intelligent selection of correct values without resorting to reset procedures, maintaining reliability while minimizing latency through targeted correction.
3Reliability
If layered error detection approach is implemented, then error correction capability is improved, but device complexity increases
Solution Approach 1:
The patent implements a dynamic error correction approach where the system adapts its correction strategy based on error detection results. SECDED handles simple cases quickly, while CRC-based candidate generation is activated only when needed for uncorrectable errors. This dynamic behavior improves correction capability without proportionally increasing complexity.
Solution Approach 2:
The patent changes the operational parameters of error detection based on detected error patterns. When SECDED detects uncorrectable errors, the system switches to CRC-based candidate generation with different validation parameters. This parameter adaptation allows the system to handle diverse error types effectively without requiring a completely complex system design.
Data Source
AI summary
Methods, systems, and devices for memory error correction based on layered error detection are described. In some examples, a memory system identifies, based on a first type of error detection procedure, that a set of bits includes a quantity of erroneous bits that is uncorrectable based on the first type of error detection procedure alone. The memory system generates one or more candidate sets of bits based on altering different groups of bits within the set of bits and evaluate one or more such candidate sets of bits using a second type of error detection procedure until a candidate set of bits is identified as error-free. The memory system then corrects the set of bits based on the candidate set of bits identified as error-free.