Layered Memory Error Correction for SECDED Overflow
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory systems face challenges in correcting uncorrectable errors detected by single error correcting and dual error detecting (SECDED) procedures, leading to undesirable latencies and reliability issues when errors exceed the correctable limit.
Innovation Solution
Implementing a layered error detection approach by using a second error detection procedure, such as a cyclic redundancy check (CRC), on a broader set of bits that includes the initially detected erroneous bits and additional bits, to generate candidate sets and identify error-free alternatives, thereby correcting errors without resorting to reset procedures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If SECDED procedure is used for error detection, then error detection capability is improved, but error correction capability deteriorates when errors exceed single-bit limits
Solution Approach 1:
The error correction process is segmented into multiple stages: first SECDED detects the error, then CRC identifies the erroneous bits, and finally a candidate generation and evaluation process corrects them. This segmentation allows each component to specialize in its strength while collectively achieving comprehensive error correction.
Solution Approach 2:
The patent introduces an intermediary CRC check between error detection and correction. The CRC acts as a mediator that identifies which specific bits are erroneous, enabling precise correction without requiring a complete reset procedure.
2Reliability
If reset procedure is initiated for uncorrectable errors, then system reliability is improved, but latency increases significantly
Solution Approach 1:
The patent performs preliminary error analysis using CRC before initiating a reset procedure. By pre-identifying correctable errors through the layered detection approach, the system can correct errors in-place without triggering time-consuming reset sequences, thus reducing latency while maintaining reliability.
Solution Approach 2:
Instead of always performing a complete reset procedure for any detected error, the patent applies partial correction actions only to the specific erroneous bits identified by CRC. This selective approach corrects sufficient errors without the overhead of a full system reset, reducing latency while achieving the necessary reliability.
3Reliability
If command is aborted for uncorrectable errors, then data integrity is improved, but productivity deteriorates due to lost operations
Solution Approach 1:
The patent implements a feedback mechanism where the CRC check provides information about the nature and location of errors. This feedback enables the system to determine whether correction is possible before aborting the command, allowing productive continuation of operations when correction succeeds while maintaining data integrity when correction fails.
Solution Approach 2:
The patent changes the parameter of error handling from binary (abort or reset) to a spectrum of responses based on error characteristics. By analyzing error patterns through CRC and generating candidate corrections, the system adapts its response based on the specific error parameters, maintaining productivity for correctable errors while protecting integrity for uncorrectable ones.
Data Source
AI summary
Methods, systems, and devices for memory error correction based on layered error detection are described. In some examples, a memory system identifies, based on a first type of error detection procedure, that a set of bits includes a quantity of erroneous bits that is uncorrectable based on the first type of error detection procedure alone. The memory system generates one or more candidate sets of bits based on altering different groups of bits within the set of bits and evaluate one or more such candidate sets of bits using a second type of error detection procedure until a candidate set of bits is identified as error-free. The memory system then corrects the set of bits based on the candidate set of bits identified as error-free.