Layered Mold CTE Mismatch for Semiconductor Warpage Control

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Semiconductor packages face warpage issues due to mechanical stresses and thermal expansion/contraction during manufacturing and operation, particularly in panelized processing where multiple dies are manufactured on a common carrier, and this warpage can lead to fractures in internal conductors and disrupt manufacturing processes.

Innovation Solution

A semiconductor package design featuring a layered mold with a fiber layer separating two resin layers of different coefficients of thermal expansion (CTE), where the CTE of one resin layer is higher than the other, and using a flexible carrier during manufacturing to mitigate stress, which helps balance thermal expansion and contraction, reducing warpage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a single resin layer is used in the mold, then the manufacturing process is simple, but package warpage occurs due to thermal expansion and contraction

Engineering Contradiction:
Improvemold structure simplicityVSAvoidpackage warpage
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The mold is segmented into multiple resin layers with different CTE values, where each layer contributes differently to thermal expansion behavior. This segmentation allows the mold to compensate for warpage through differential expansion while maintaining manufacturing feasibility through layer-by-layer construction

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The mold uses composite material construction with multiple resin layers having different coefficients of thermal expansion. This composite structure creates a balanced thermal response that mitigates warpage during temperature cycling in manufacturing and operation

Inventive Principle:
Principle #40Composite materials

2Strength

If a stiff carrier is used during manufacturing, then the carrier provides structural support, but stress is applied to the semiconductor packages during carrier removal

Engineering Contradiction:
Improvecarrier structural supportVSAvoidstress on packages
Core Design Contradiction:
StrengthVSObject-affected harmful factors

Solution Approach 1:

The carrier uses a flexible membrane structure that provides sufficient structural support during manufacturing processes while allowing stress-free removal from the molded packages. The flexibility enables the carrier to deform during ejection without transmitting damaging stress to the semiconductor packages

Inventive Principle:
Principle #30Flexible shells and thin films

3Stability of the object's composition

If resin layers with similar CTE are used, then the mold structure is uniform, but thermal expansion and contraction cause warpage

Engineering Contradiction:
Improvemold structure uniformityVSAvoidpackage warpage
Core Design Contradiction:
Stability of the object's compositionVSReliability

Solution Approach 1:

Different resin layers are assigned different CTE values tailored to their specific positions and functional requirements. The first resin layer has CTE matched to the semiconductor die for stable bonding, while the second resin layer has different CTE to compensate for overall mold warpage, creating local optimization throughout the structure

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively minimizes warpage in semiconductor packages during manufacturing and operation, enhancing the robustness of electrical connections and reducing the risk of fractures, thereby improving the reliability of the packages.

Implementation Method 1

The layered mold includes a fiber layer along a backside of the semiconductor die. The fiber layer separates two resin layers, which have substantially different coefficients of thermal expansion (CTE). For example, the CTE of the resin layer adjacent the semiconductor die may be higher than the CTE of the resin layer on the opposite side of the fiber layer.

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS10879144B2Semiconductor package with multilayer mold
Publication Date: 2020.12.29 TEXAS INSTRUMENTS INC
  • US10879144B2 patent drawing
  • US10879144B2 patent drawing
  • US10879144B2 patent drawing

AI summary

A semiconductor package includes a semiconductor die including an active side, a redistribution layer over the active side of the semiconductor die, the redistribution layer including metal traces electrically connecting die pads on the active side of the semiconductor die to electrical contacts on an external surface of the semiconductor package, and a layered mold covering the semiconductor die opposite the redistribution layer. The layered mold includes a first resin layer adjacent to the redistribution layer, a fiber layer adjacent to the first resin layer and opposite the redistribution layer, and a second resin layer adjacent to the fiber layer and opposite the redistribution layer. A coefficient of thermal expansion (CTE) of the first resin layer is substantially different than a CTE of the second resin layer.