Layered MTJ SRAM Cells for Non-Volatile, Low-Leakage Storage
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Solution Overview
Problem
Existing memory devices face challenges in achieving high storage density and power efficiency, particularly in non-volatile memory devices, due to the use of P-type transistors which consume more area and generate leakage current.
Innovation Solution
A memory cell design incorporating N-type transistors and magnetic tunnel junction (MTJ) devices in different layers, bypassing P-type transistors, which allows for area-efficient and power-efficient non-volatile memory operation by using MTJ devices to store data without power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If P-type transistors are used in memory devices, then non-volatile data storage is achieved, but area efficiency deteriorates and leakage current increases
Solution Approach 1:
The patent extracts and removes P-type transistors from the memory cell structure, replacing them entirely with N-type transistors. This extraction eliminates the harmful characteristics of P-type transistors (large area, high leakage) while maintaining the non-volatile data storage function through the MTJ devices and modified circuit topology.
Solution Approach 2:
The patent changes the fundamental parameter of transistor type from P-type to N-type throughout the memory cell. This parameter change fundamentally alters the electrical characteristics, reducing both area consumption and leakage current while maintaining functionality through the regenerative latch circuit design.
2Reliability
If P-type transistors are used in memory devices, then non-volatile data storage is achieved, but power efficiency deteriorates due to leakage current
Solution Approach 1:
The patent extracts and removes P-type transistors from the memory cell structure, replacing them entirely with N-type transistors. This extraction eliminates the harmful characteristics of P-type transistors (large area, high leakage) while maintaining the non-volatile data storage function through the MTJ devices and modified circuit topology.
Solution Approach 2:
The patent converts the potential harm of using only N-type transistors (which traditionally cannot maintain stable logic states) into a benefit by employing MTJ devices with high resistance states to maintain logic levels, thereby achieving both low leakage and stable data retention.
3Loss of energy
If MTJ devices are used for data storage, then power efficiency is improved, but device complexity increases due to multi-layer structure
Solution Approach 1:
The patent moves the data storage function from the planar transistor layer to a vertical multi-layer MTJ structure. By utilizing the vertical dimension with pinned layers, barrier layers, and free layers stacked perpendicular to the substrate, the design achieves area-efficient storage while consolidating the storage function in a compact vertical footprint.
Solution Approach 2:
The MTJ devices serve multiple functions simultaneously: they act as non-volatile memory elements, as resistive components for logic state representation, and as part of the regenerative latch circuit. This multi-functionality reduces the need for separate components, thereby managing overall device complexity despite the multi-layer structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves improved storage density and power efficiency by eliminating P-type transistors, reducing leakage current, and enabling non-volatile data storage without continuous power consumption.
Implementation Method 1
magnetic tunnel junction (MTJ) devices in different layers, bypassing P-type transistors, which allows for area-efficient and power-efficient non-volatile memory operation by using MTJ devices to store data without power
Data Source
AI summary
Disclosed herein are related to a memory cell including magnetic tunneling junction (MTJ) devices. In one aspect, the memory cell includes a first layer including a first transistor and a second transistor. In one aspect, the first transistor and the second transistor are connected to each other in a cross-coupled configuration. A first drain structure of the first transistor may be electrically coupled to a first gate structure of the second transistor, and a second drain structure of the second transistor may be electrically coupled to a second gate structure of the first transistor. In one aspect, the memory cell includes a second layer including a first MTJ device electrically coupled to the first drain structure of the first transistor and a second MTJ device electrically coupled to the second drain structure of the second transistor. In one aspect, the second layer is above the first layer.