Layered 3D NAND Channel Structure Narrowing via Wet Oxidation
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Solution Overview
Problem
3D NAND flash memory devices face reliability issues due to aggressive scaling, leading to fabrication errors and reduced yield rates, which are not effectively addressed by existing technologies.
Innovation Solution
A fabrication method is employed to form a semiconductor structure with layers of polysilicon, silicon oxide, and silicon nitride, utilizing a wet oxidation process to expand and narrow portions of the channel structure, and a chemical mechanical polishing process to remove sacrificial layers, enhancing reliability and reducing fabrication errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar memory cells are scaled down to reduce manufacturing cost and increase storage density, then storage density is improved, but reliability deteriorates due to process technology limitations
Solution Approach 1:
The patent transitions from planar (2D) memory cell architecture to three-dimensional vertically stacked memory cell architecture. Multiple layers of memory cells are stacked vertically to form memory strings, where channels are connected vertically through the stacked structure. This dimensional change allows storage density to increase significantly while maintaining larger individual cell dimensions that avoid the reliability issues associated with aggressive planar scaling.
2Manufacturing precision
If wet oxidation process is used to expand the third layer, then manufacturing precision is improved by narrowing the opening, but process complexity increases
Solution Approach 1:
The patent employs wet oxidation process to transform the third layer (polysilicon) into silicon oxide, causing volumetric expansion of the material. By controlling oxidation parameters such as temperature, time, and gas composition (H2O/O2 ratio), the process precisely controls the degree of expansion to achieve the desired opening narrowing. This parameter-based control provides manufacturing precision without requiring additional lithography or etching steps.
Solution Approach 2:
Instead of using mechanical or lithographic methods to narrow the opening, the patent substitutes a chemical process (wet oxidation) that causes controlled volumetric expansion of the polysilicon layer. This chemical transformation naturally narrows the opening as the material expands in-place, replacing complex mechanical alignment and patterning operations with a self-contained chemical transformation process.
3Reliability
If channel structure is narrowed to improve reliability, then data integrity is improved, but fabrication difficulty increases
Solution Approach 1:
The patent performs the narrowing action during the formation of the channel structure itself, rather than as a subsequent modification step. The wet oxidation process is applied to the polysilicon layer before final channel definition, allowing the narrowing to occur as an integrated part of the fabrication sequence. This preliminary action embeds the reliability-enhancing narrowing feature into the base fabrication process without requiring additional complex steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method increases the reliability of NAND memory devices by minimizing fabrication errors, improving yield rates, and maintaining data integrity through a structured channel design.
Implementation Method 1
oxidizing the exposed portion of the third layer to form silicon oxide to expand the exposed portion of the third layer based on the oxidizing
Data Source
AI summary
The present disclosure provides a fabrication method to produce a semiconductor structure with increased reliability for use in NAND memory devices. The method can include forming a layered semiconductor structure that includes a first layer, a second layer disposed on the first layer, and a third layer disposed on the second layer. The method can also include forming a channel structure, which can include etching the first layer, the second layer, and the third layer to form an opening through a surface of the semiconductor structure. A portion of the third layer can be exposed at the opening. The forming of the channel structure also include oxidizing the exposed portion of the third layer to form silicon oxide expand the exposed portion of the third layer.