Layered Pixel Circuit Display for Narrow-Area Integration
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Solution Overview
Problem
Existing display devices with high resolution face challenges in integrating components in a narrow area, leading to complex manufacturing processes and increased costs.
Innovation Solution
A display device design with a pixel circuit layer comprising a lower transistor made of silicon semiconductor and an upper transistor made of oxide semiconductor, connected by an intermediate conductive layer that includes a data line and a power line, allowing for integration of components in a narrow area and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If components are sequentially stacked along a vertical direction to achieve high resolution integration in a narrow area, then the integration density is improved, but the manufacturing process becomes complicated and manufacturing cost increases
Solution Approach 1:
The patent merges the intermediate conductive layer with the power line layer, so that the power line and data line are formed at the same layer. This consolidation reduces the total number of manufacturing steps while maintaining the vertical stacking architecture, thereby resolving the contradiction between high integration density and manufacturing complexity
Solution Approach 2:
The intermediate conductive layer serves multiple functions: it acts as both a power line layer and a data line layer. By making this layer universal for both signal types, the patent reduces the number of separate layers needed, simplifying the manufacturing process while achieving high component integration in a narrow area
2Productivity
If more components are integrated in a narrow area to achieve high resolution, then the display device performance is improved, but the manufacturing cost increases
Solution Approach 1:
By merging the power line layer and data line layer into a single intermediate conductive layer, the patent reduces the total number of manufacturing steps. This consolidation maintains high integration efficiency while lowering manufacturing costs through process simplification
Solution Approach 2:
The patent utilizes vertical stacking (moving from 2D planar integration to 3D vertical integration) to achieve high component density in a narrow area. This dimensional change allows more components to be integrated without proportionally increasing manufacturing complexity, as the vertical arrangement shares common conductive layers
Data Source
AI summary
A display device includes a base layer, a pixel circuit layer on the base layer, the pixel circuit layer including a pixel circuit, and a light emitting layer on the pixel circuit layer, the light emitting layer including a light emitting element electrically connected to the pixel circuit, wherein the pixel circuit layer includes: a lower transistor on the base layer, the lower transistor including a silicon semiconductor, an upper transistor on the lower transistor, the upper transistor including an oxide semiconductor, and an intermediate conductive layer between the lower transistor and the upper transistor, and wherein the intermediate conductive layer includes a data line and a first power line, each of which is electrically connected to the pixel circuit.