Layered Pixel Interconnects for High-Definition Display Reliability
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Solution Overview
Problem
In display devices with reduced pixel size for high definition and small-sized electronic devices, issues such as noise interference, luminance uniformity deterioration, short circuits, and interconnection failures occur due to increased parasitic capacitance and dense interconnection layouts, affecting reliability.
Innovation Solution
The display device is configured with scanning and signal lines in orthogonal interconnection layers, where one type of line with more lines is positioned in a lower-level layer, allowing for a sparser interconnection pattern and improved electrode area, enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pixel size is reduced to achieve higher definition in small-sized electronic apparatus, then display definition is improved, but parasitic capacitance between interconnections increases causing noise interference and luminance uniformity deterioration
Solution Approach 1:
The patent applies dimensional change by separating scanning lines and signal lines into different interconnection layers (vertical stacking). This transforms the two-dimensional planar layout into a three-dimensional layered structure, reducing parasitic capacitance between lines while maintaining dense pixel arrangement for high definition.
Solution Approach 2:
The patent segments the interconnection system by dividing scanning lines and signal lines into separate layers. This segmentation isolates the signal paths, reducing electromagnetic interference and parasitic capacitance between adjacent lines, thereby solving the noise interference problem in high-density pixel arrangements.
2Measurement precision
If pixel size is reduced to achieve higher definition, then display definition is improved, but interconnection density increases causing short circuits and interconnection failures
Solution Approach 1:
By transitioning from planar to vertical interconnection arrangement through layered stacking, the patent reduces the density of interconnections within each layer. This dimensional change allows for larger spacing between lines in each layer, improving reliability by reducing short circuit risks while maintaining overall high definition through vertical integration.
3Device complexity
If electrode area of capacitance element is reduced due to dense interconnection pattern, then device complexity is reduced, but noise resistance deteriorates
Solution Approach 1:
The patent places the capacitance element electrode in an interconnection layer with sparser pattern, utilizing the vertical dimension to separate the electrode from dense interconnection lines. This allows sufficient electrode area in a layer with reduced line density, improving noise resistance while maintaining overall device complexity through efficient spatial utilization.
Data Source
AI summary
Display devices are disclosed. In one example, a display device includes pixel circuits arranged in a matrix. Each of the pixel circuits including a light emitting element and a driving circuit for driving the light emitting element. Scanning lines are connected to the respective pixel circuits and extend in a row direction. Signal lines are connected to the pixel circuits and extend in a column direction. One of the scanning lines or the signal lines are positioned in a lower level interconnection layer. An electrode of a capacitance element included in the driving circuit is positioned in the interconnection layer in which either the scanning lines or the signal lines are provided.