Layered Power Module Structure for Chip Hot Spot Cooling
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Solution Overview
Problem
High-power chips installed on ceramic substrates with thin copper layers experience local hot spots, making it difficult for heat to dissipate effectively due to limited thermal conductivity and warpage issues.
Innovation Solution
A power module structure is introduced, featuring a copper layer on a substrate with additional metal layers of high thermal conductivity, such as copper, silver, or aluminum, placed under or around the chip to enhance heat dissipation by increasing the heat transfer area and reducing warpage, while being connected to the copper layer on the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a thin copper layer is used on the ceramic substrate, then the substrate maintains good electrical insulation and processability, but local hot spots are generated and heat dissipation becomes difficult
Solution Approach 1:
The patent applies local quality by creating a multi-layer copper structure where the first copper layer is thin (for substrate coverage) and the second copper layer is thick (for heat dissipation). This localized thickening directly addresses the hot spot problem without requiring the entire copper layer to be thick, thus resolving the contradiction between heat dissipation needs and process control complexity.
Solution Approach 2:
The patent uses composite materials by combining multiple copper layers with different thicknesses on the ceramic substrate. The composite structure of thin first copper layer plus thick second copper layer creates a system that simultaneously achieves good electrical insulation (from the thin first layer) and effective heat dissipation (from the thick second layer).
2Temperature
If the copper layer is made thicker to improve heat dissipation, then local hot spots are reduced, but etching ability deteriorates and warpage increases
Solution Approach 1:
The patent segments the copper layer into two distinct layers: a first copper layer that is thin and provides good etching ability and warpage control, and a second copper layer that is thick and provides excellent heat dissipation. This segmentation allows each layer to optimize its function without compromising the other, resolving the contradiction between heat dissipation and manufacturing precision.
Solution Approach 2:
The patent resolves the contradiction by adding a vertical dimension to the copper structure. Instead of using a single thick layer, it creates a multi-layer vertical structure where the first copper layer remains thin for processability and the second copper layer is thick for heat dissipation. This dimensional approach allows simultaneous optimization of both etching ability and heat dissipation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves uniform heat dissipation, reduces substrate warpage, and conserves copper material by amplifying the heat source's thermal conductivity and expanding the heat dissipation area, effectively cooling high-power chips.
Implementation Method 1
an additional metal layer with high thermal conductivity and electrical conductivity is placed under (or around) the chip to partially thicken the copper layer on the substrate, which promotes heat to be evenly transferred on the metal layer first and expands the heat dissipation area, and then conducts more efficient heat transfer downwards
Implementation Method 2
promotes heat to be evenly transferred on the metal layer first and expands the heat dissipation area
Data Source
Figure 1~2A
Figure 2B~2C
Figure 3
AI summary
A power module structure is provided. The power module structure includes a substrate, a copper layer, a metal layer, and a chip. The copper layer is disposed on the substrate. The metal layer is disposed on the copper layer. The area of the metal layer is smaller than that of the copper layer. The chip is disposed on the metal layer. The area of the chip is smaller than that of the metal layer.