Layered Semiconductor Package Layout for Thin PoP Warpage Control
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Solution Overview
Problem
Semiconductor packages face challenges in being both thin and light while maintaining structural reliability and heat dissipation efficiency, particularly in package-on-package configurations where warpage and redistribution line patterns need improvement.
Innovation Solution
A semiconductor package design featuring a redistribution structure with conductive studs and posts, adhesive layers, and molding layers that reduce warpage and enhance heat dissipation, along with a method of manufacturing that includes forming redistribution patterns and molding layers to connect semiconductor chips efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Weight of moving object
If the semiconductor package is made thin and light, then the weight and thickness are reduced, but the structural reliability deteriorates due to warpage
Solution Approach 1:
The package structure is divided into multiple functional layers including first and second redistribution structures, molding layers, adhesive layers, and conductive elements. This segmentation allows each layer to perform specific functions while distributing mechanical stress, thereby maintaining structural reliability in thin packages
Solution Approach 2:
The package employs composite material structures combining semiconductor chips, molding compounds, adhesive layers, and conductive materials in a stacked configuration. This composite approach enables the thin package to achieve both reduced weight and maintained structural integrity through material property optimization
2Area of moving object
If the redistribution line patterns are made finer, then the device density is increased, but the manufacturing precision deteriorates
Solution Approach 1:
The redistribution structures are formed extending in vertical directions between first and second surfaces of the semiconductor chip, adding a vertical dimension to the traditional planar redistribution. This three-dimensional approach allows finer horizontal patterns while maintaining manufacturability through vertical stacking
Solution Approach 2:
Multiple redistribution structures are nested within each other in a stacked configuration, with first and second redistribution structures positioned at different vertical levels. This nesting enables high-density interconnection through vertical integration rather than horizontal expansion, preserving manufacturing precision
3Adaptability or versatility
If package-on-package configuration is implemented, then the functional integration is improved, but the warpage increases
Solution Approach 1:
The package structure incorporates conductive studs and posts that extend through molding layers and connect different stacked packages. These rigid conductive elements act as structural counterweights that resist warpage forces generated by thermal expansion mismatches in the package-on-package configuration
Solution Approach 2:
The molding layers are configured with specific properties in different regions: first molding layers surround conductive studs while second molding layers surround conductive posts. This localized quality variation allows differential stress management in different areas of the stacked package, reducing overall warpage
4Temperature
If the heat dissipation efficiency is improved, then the thermal management is enhanced, but the device complexity increases
Solution Approach 1:
The conductive studs and posts serve multiple functions: they provide electrical interconnection between stacked packages and simultaneously act as heat dissipation pathways. This multi-functionality improves thermal management without adding separate dedicated thermal management structures, thereby limiting complexity increase
Data Source
AI summary
Disclosed is a semiconductor package including a semiconductor chip having a first surface adjacent to an active layer and a second surface opposite to the first surface; a conductive stud disposed on the first surface of the semiconductor chip and connected to the active layer; an adhesive layer disposed on the second surface of the semiconductor chip; a conductive post disposed outside the semiconductor chip; a first redistribution structure, which is on the first surface of the semiconductor chip and includes a first redistribution insulation layer supporting the conductive stud and the conductive post; a second redistribution structure, which is on the second surface of the semiconductor chip and includes a second redistribution insulation layer disposed on the adhesive layer; and a first molding layer disposed on the first redistribution structure and surrounding the semiconductor chip, the adhesive layer, the conductive stud, and the conductive post.