Layered SiC Substrate Structure to Prevent GaN Epitaxial Cracking
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Solution Overview
Problem
The high cost of manufacturing nitride semiconductor devices is exacerbated by the need for high-cost via hole formation in SiC substrates, which can lead to warping and internal cracking of the nitride epitaxial layer due to thickening required to reduce parasitic capacitance when using conductive SiC substrates.
Innovation Solution
A nitride semiconductor device structure incorporating a low resistance SiC layer and a high resistance SiC layer on the SiC substrate, with a nitride epitaxial layer disposed on the high resistance SiC layer, and a manufacturing method that includes forming these layers to suppress warping and cracking, where the low resistance SiC layer has a resistivity of not more than 0.01 Ω·cm and the high resistance SiC layer has a resistivity of not less than 10 Ω·cm, and the nitride epitaxial layer is kept thin to prevent structural issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conductive SiC substrate is used to stabilize ground, then electrical stability is improved, but the nitride epitaxial layer must be thickened which causes warping of the SiC substrate and internal cracking
Solution Approach 1:
The SiC substrate is segmented into multiple functional layers: a conductive SiC substrate layer for electrical stability, a low-resistivity SiC layer for enhanced electrical connection, and a high-resistivity SiC layer for mechanical support. This segmentation allows each layer to specialize in its function, preventing the need to thicken the entire substrate which would cause warping and cracking.
Solution Approach 2:
Different regions of the SiC structure are assigned different resistivity characteristics. The lower SiC layer has low resistivity (≤0.01 Ω·cm) for electrical conduction, while the upper SiC layer has high resistivity (≥10 Ω·cm) for mechanical support and parasitic capacitance reduction. This local differentiation resolves the contradiction between electrical stability and structural integrity.
2Reliability
If via holes are formed in the SiC substrate for electrical connection, then electrical connectivity is improved, but manufacturing cost increases significantly
Solution Approach 1:
The patent extracts the via hole formation step from the manufacturing process by providing a conductive SiC substrate with pre-formed electrical connection structures. The low-resistivity SiC layer is continuously formed over the substrate surface, eliminating the need for costly via hole etching, filling, and planarization processes while maintaining electrical connectivity.
Solution Approach 2:
The patent replaces the expensive via hole formation process with a simpler, more cost-effective approach using low-resistivity SiC layers that can be formed using standard epitaxial growth techniques. This substitutes a complex, high-cost process with a simpler, lower-cost alternative that achieves the same electrical connection function.
3Reliability
If the nitride epitaxial layer is thickened to reduce parasitic capacitance, then electrical performance is improved, but internal cracking occurs in the layer
Solution Approach 1:
The patent applies local quality by creating a high-resistivity SiC layer specifically positioned between the conductive substrate and the nitride epitaxial layer. This layer has resistivity ≥10 Ω·cm which reduces parasitic capacitance without requiring thickening of the nitride epitaxial layer itself, thereby preventing internal cracking while achieving the desired electrical performance.
Data Source
AI summary
A nitride semiconductor device includes an SiC substrate having a first principal surface and a second principal surface at an opposite side thereto, a low resistance SiC layer that is formed on the first principal surface and is lower in resistivity than the SiC substrate, a high resistance SiC layer that is formed on the low resistance SiC layer and is higher in resistivity than the low resistance SiC layer, and a nitride epitaxial layer that is disposed on the high resistance SiC layer.