Layered Source/Drain Contacts for Lower Parasitic Resistance
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Solution Overview
Problem
As integrated circuit technologies progress towards smaller technology nodes, parasitic resistance in source/drain contacts of semiconductor devices increases due to reduced landing areas and trapped voids, degrading the electrical performance of IC devices.
Innovation Solution
A method is introduced to form a two-layer source/drain contact structure, where a silicide layer with a flat top surface is formed over the source/drain feature, followed by a tungsten layer with a convex top surface, and then a metal layer (such as cobalt, ruthenium, or molybdenum) is deposited using physical vapor deposition and chemical vapor deposition processes, respectively, to increase the landing area and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing source/drain contacts are used, then the device structure is simple, but parasitic resistance increases due to reduced landing areas and trapped voids
Solution Approach 1:
The source/drain contact is divided into multiple distinct layers: a silicide layer directly over the source/drain feature, a tungsten-containing layer over the silicide layer, and a conductive layer over the tungsten-containing layer. This segmentation allows each layer to perform specific functions - the silicide layer provides low resistance contact to the source/drain feature, the tungsten layer provides structural support and additional conduction path, and the conductive layer provides the final electrical connection. By dividing the contact into separate functional layers rather than using a single material, the patent reduces parasitic resistance while maintaining manufacturability.
2Productivity
If the contact area is reduced to increase device density, then productivity increases, but parasitic resistance increases due to smaller landing areas
Solution Approach 1:
The patent extends the contact structure vertically by adding multiple layers stacked on top of each other. Instead of increasing the horizontal landing area, the solution adds depth to the contact structure with the silicide layer, tungsten-containing layer, and conductive layer stacked vertically. This dimensional transition from 2D area expansion to 3D vertical stacking allows the horizontal footprint to remain small (maintaining device density) while the vertical stacking provides multiple conduction paths that reduce parasitic resistance.
3Ease of manufacture
If conventional deposition processes are used, then the manufacturing process is simple, but voids are trapped in the contact structure increasing resistance
Solution Approach 1:
The silicide layer is formed first as a preliminary step before depositing the tungsten-containing layer and conductive layer. This preliminary silicide layer serves multiple purposes: it provides a low-resistance contact to the source/drain feature, creates a flat surface that facilitates subsequent deposition, and prevents void formation by establishing a solid foundation. By performing this preparatory action of forming the silicide layer first, the patent eliminates void trapping issues that would occur if deposition were done directly onto the source/drain feature, while still using conventional deposition processes for the subsequent layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic resistance and improves the electrical performance of IC devices by minimizing voids and enhancing the contact area between the source/drain contacts and the silicide layer.
Implementation Method 1
forming a silicide layer in the contact opening and on the source/drain feature
Implementation Method 2
forming a tungsten-containing layer in the contact opening and on the silicide layer
Implementation Method 3
forming a conductive layer in the contact opening and on the tungsten-containing layer, a composition of the conductive layer is different from a composition of the tungsten-containing layer
Data Source
AI summary
Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary method includes receiving a workpiece comprising a channel region over a substrate, a source/drain feature adjacent the channel region, a gate structure over the channel region, and a dielectric structure over the source/drain feature. The method also includes forming a contact opening penetrating through the dielectric structure to expose the source/drain feature, forming a silicide layer in the contact opening and on the source/drain feature, forming a tungsten-containing layer in the contact opening and on the silicide layer, and forming a conductive layer in the contact opening and on the tungsten-containing layer, where a composition of the conductive layer is different from a composition of the tungsten-containing layer.