Layered TFT Channel Structure for Mobility and Process Stability
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Solution Overview
Problem
Conventional transistors face challenges with high-mobility materials in thin-film transistors (TFTs) prone to defects during processing, leading to reduced gate control and performance issues due to exposure to high temperatures and detrimental conditions, and passivation layers can impact channel performance.
Innovation Solution
A multi-layered channel structure is implemented in transistors, with higher-mobility layers near the gate and lower-mobility layers farther away, using materials like indium oxide, tin oxide, and insulating oxides or nitrides, and treatments such as gas and heat processes to enhance stability and mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high-mobility materials are used in thin-film transistor channels, then carrier mobility is improved, but the materials are prone to defects during processing due to exposure to high temperatures and detrimental conditions
Solution Approach 1:
The channel is divided into multiple layers with different materials and functions. The lower channel layer uses high-mobility material close to the gate for performance, while the upper channel layer uses more stable material for processing robustness. This segmentation allows each layer to optimize for its specific role.
Solution Approach 2:
Different regions of the channel are assigned different material properties. The lower channel layer near the gate has high mobility for effective control, while the upper channel layer has higher stability for processing. Each local region is optimized for its specific functional requirements.
2Reliability
If passivation layers are added to protect the channel, then stability is improved, but the passivation layers can impact channel performance
Solution Approach 1:
The protective function is extracted from a separate passivation layer and integrated into the upper channel layer itself. The upper channel layer serves dual purposes: maintaining channel performance and providing inherent protection during processing, eliminating the need for additional passivation layers that would compromise performance.
3Reliability
If a multi-layered channel structure is implemented, then defects are reduced and gate control is improved, but device complexity increases
Solution Approach 1:
The multi-layer channel structure is self-forming through sequential deposition processes. The lower channel layer is deposited first, then the upper channel layer is deposited on top, with each layer self-aligning to the gate structure. This self-service approach reduces the need for complex alignment steps and tooling.
Data Source
AI summary
A thin-film transistor has a channel region with multiple thin-film layers. The transistor has a gate at one side (e.g., at the bottom) and two source/drain contacts on the opposite side (e.g., at the top). One or more channel layers closer to the gate (e.g., lower channel layers) have a higher mobility than one or more channel layers farther from the gate (e.g., upper channel layers). Reducing mobility near the top of the device increases stability of the channel during additional processing.