Layered Wiring Board Pads for Multi-Size Chip Mounting
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Solution Overview
Problem
Existing semiconductor packages face challenges in miniaturization and versatility due to the fixed size and arrangement of connection pads, which limits their ability to accommodate chip components of varying sizes without requiring redesign of the wiring board.
Innovation Solution
The proposed wiring board structure includes multiple pad regions with different sizes arranged in various layers, allowing for the selective mounting of chip components of varying sizes without necessitating a new wiring board, thereby enhancing versatility and reducing the size of the mounting regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the wiring board has fixed size and arrangement of connection pads, then the manufacturing process is simple, but the versatility to accommodate chip components of varying sizes is limited
Solution Approach 1:
The wiring board is divided into multiple pad regions (first pad region, second pad region, third pad region) with different sizes and arrangements. Each pad region can independently accommodate chip components of different sizes, allowing the same wiring board to support various chip configurations without redesign.
Solution Approach 2:
The wiring board is designed with multiple pad regions that can serve different functions - some regions accommodate larger chips while others accommodate smaller chips. This multi-functional design allows a single wiring board to replace multiple specialized boards, enhancing versatility while maintaining manageable complexity through standardized structures.
2Adaptability or versatility
If the wiring board is designed to accommodate various chip sizes, then the versatility improves, but the occupancy area increases
Solution Approach 1:
The patent utilizes the vertical dimension by arranging pad regions at different heights and depths within the wiring board structure. Multiple pad regions are positioned in different layers, allowing efficient use of three-dimensional space rather than spreading out horizontally, thus reducing the overall occupancy area while maintaining versatility.
Solution Approach 2:
Smaller pad regions are positioned within or adjacent to larger pad regions, allowing efficient spatial arrangement. The nested configuration enables multiple chip sizes to be accommodated in a compact layout, reducing the total occupancy area while maintaining the ability to support various chip component sizes.
3Area of stationary object
If multiple pad regions with different sizes are arranged in various layers, then the occupancy area is reduced, but the manufacturing complexity increases
Solution Approach 1:
The wiring board is designed with pre-defined pad regions at different layers with standardized dimensions and positions. This preliminary structuring allows for systematic manufacturing processes where each layer can be fabricated independently using standard techniques, reducing the overall manufacturing complexity despite the multi-layered structure.
Data Source
AI summary
A wiring board includes: a first insulating layer; a first pad region provided above the first insulating layer and having a first connection pad; a second insulating layer provided above the first connection pad and having a first opening to expose the first connection pad; a second pad region provided above the second insulating layer and having a second connection pad electrically connected to the first connection pad; and a third insulating layer provided above the second connection pad, and having a second opening to exposes the first and second connection pads. The first connection pad region is smaller than the second connection pad region.