Layout Adaptive Word Line Detection in Non-Volatile Memory
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Solution Overview
Problem
Existing non-volatile memory systems face challenges in detecting short circuits involving word lines, which can lead to functional defects and data loss, especially in three-dimensional memory structures where defects can affect multiple blocks and cause plane-level failures.
Innovation Solution
The proposed solution involves a layout adaptive approach for detecting problematic word lines. This method includes introducing high voltage switches to bias layout-specific control lines, allowing for the identification of current leakage between adjacent local supply lines and global supply lines, thereby marking defective dies at the plane level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional defect detection methods are used in non-volatile memory, then manufacturing process is simple, but detection precision is insufficient to identify layout-specific problematic word lines
Solution Approach 1:
The patent applies preliminary action by performing defect detection during the manufacturing process rather than after device completion. The detection circuit is integrated into the memory structure and activates word lines with specific voltages to detect short circuits before the device is shipped, enabling early identification of problematic word lines without requiring complex external testing equipment.
Solution Approach 2:
The patent introduces an intermediary detection circuit that mediates between the memory cells and the external testing environment. This circuit includes detection transistors and control logic that interface with word lines and bit lines, enabling precise detection of layout-specific defects without exposing the entire memory system to complex external test equipment.
2Reliability
If comprehensive defect detection is performed on all word lines, then reliability is improved, but productivity decreases due to increased testing time
Solution Approach 1:
The patent applies local quality by focusing detection efforts on specific problematic word lines identified through layout analysis rather than uniformly testing all word lines. The detection circuit targets word lines that are adjacent to global supply lines in the metal layout, concentrating testing resources on high-risk areas while reducing overall testing time and maintaining high reliability.
Solution Approach 2:
The patent changes the voltage parameter applied to word lines during detection. Detection transistors activate word lines with specific voltages (e.g., Vpp or Vcc) that differ from normal operation voltages, enabling the detection of short circuits that may not manifest under standard operating conditions. This parameter change allows comprehensive reliability checking without requiring exhaustive testing scenarios.
3Measurement precision
If layout-specific detection is implemented to identify problematic word lines, then measurement precision is improved, but device complexity increases due to additional control circuits
Solution Approach 1:
The patent merges the detection function with existing memory control circuits. Detection transistors are integrated alongside normal memory access transistors, and the detection logic reuses existing word line and bit line infrastructure. This combining approach enables precise layout-specific defect detection without adding separate dedicated testing circuits, thereby limiting the increase in device complexity.
Solution Approach 2:
The patent implements multi-functionality by designing detection circuits that can operate during both manufacturing testing and potential runtime diagnostics. The same detection transistors and control logic that identify problematic word lines during manufacturing can potentially be reused for runtime error detection, maximizing the utility of the added circuitry and reducing the net complexity increase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively detects short circuits and other defects in word lines, preventing data loss and plane-level failures by identifying and isolating defective blocks early in the manufacturing process or during device operation.
Implementation Method 1
Each block in the memory array is connected to two sets of bond pads through a set of word line switches. The word line switches have first input terminals connected to a first set of voltage sources and second input terminals connected to word lines extending across the memory array.
Data Source
AI summary
In addition to word line related short circuits within the blocks of the array structure of a non-volatile memory device, such as NAND memory, word line related shorts can also occur in the routing for supplying the word lines of the memory blocks. Depending on the layout of the routing, some shorts for the word lines associated with one block can affect other blocks of the memory array. In particular, if the routing of a pair of adjacent local supply lines are adjacent to a global supply line, a short between the pair of adjacent local supply lines for one block can lead, through the global supply line, to defects in another of the block. Techniques are presented for detecting these layout related problematic word lines.