Semiconductor Layout Analysis Using Polygon Hashing

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Solution Overview

Problem

Current layout analysis methods in semiconductor manufacturing are inefficient in analyzing layouts and masks, leading to suboptimal pattern transfer and potential defects in the semiconductor process.

Innovation Solution

A layout analysis method that segments the layout pattern into rectangles, extracts conversion characteristic values by applying tolerance to shape information, calculates total hash values, groups patterns based on these values, and extracts unique patterns from each group.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If current layout analysis methods are used, then the analysis process is simple, but the analysis efficiency is low and pattern coverage is insufficient

Engineering Contradiction:
Improvelayout analysis efficiencyVSAvoidanalysis method complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The layout pattern is segmented into multiple rectangular polygons, and each polygon is assigned a hash value based on its shape characteristics. This segmentation approach enables efficient classification of patterns by grouping similar polygons together, significantly improving layout analysis efficiency while maintaining manageable complexity through systematic categorization

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The method applies tolerance-based parameter adjustments to shape characteristics when calculating hash values. By modifying the parameter extraction process to include tolerance application, the system achieves better pattern matching and coverage without requiring fundamentally complex analysis algorithms

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If traditional pattern classification methods are used, then the process is straightforward, but the number of unique patterns remains high and accuracy is limited

Engineering Contradiction:
Improvepattern classification accuracyVSAvoidnumber of unique patterns
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

Instead of directly analyzing and comparing complex layout patterns, the method creates simplified hash value representations (copies) of each polygon's shape characteristics. These hash copies enable efficient comparison and grouping, reducing the number of unique patterns identified while improving classification accuracy through consistent hashing of shape features

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The method merges multiple shape characteristics (width, height, orientation) into a single composite hash value for each polygon. By combining these parameters into unified hash representations, the system reduces the quantity of unique patterns while maintaining accurate classification through the integrated information in each hash value

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20250173477A1Layout analysis method and mask manufacturing method including the layout analysis method
Publication Date: 2025.05.29 SAMSUNG ELECTRONICS CO LTD
  • US20250173477A1 patent drawing
  • US20250173477A1 patent drawing
  • US20250173477A1 patent drawing

AI summary

A layout analysis method includes segmenting a layout pattern into a plurality of polygons in a shape of a rectangle, extracting a conversion characteristic value by applying tolerance to a characteristic value, the characteristic value comprising shape information of each of the plurality of polygons, extracting a total hash value of each of the plurality of polygons by using the conversion characteristic value of each of the plurality of polygons, grouping patterns of the plurality of polygons into a plurality of groups based on the total hash value of each of the plurality of polygons, and extracting a unique pattern from each of the groups.