Layout Analysis Using Unit Cell Classification and Pattern Propagation
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Solution Overview
Problem
The increasing complexity and miniaturization of circuit designs in photolithography pose challenges in faithfully reproducing intended layouts on substrates, leading to optical proximity effects and high computational costs for design verification, which are resource-intensive and time-consuming.
Innovation Solution
A method that identifies unit cells in a circuit design, classifies them, and propagates process results from unique patterns to other cells, reducing the need for extensive computations by using a hierarchical database and machine learning techniques to optimize layout processing and verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If design verification is performed on the entire layout, then manufacturing precision is improved, but processing time and memory requirements increase significantly
Solution Approach 1:
The layout design is divided into multiple unit cells, each representing a repeating geometric structure. Points of interest are designated for each unit cell, and the layout is classified into multiple classifications based on these points. This segmentation allows verification to be performed on representative samples rather than the entire layout, significantly reducing processing time while maintaining verification accuracy.
Solution Approach 2:
Process results obtained from verifying unique patterns of unit cells are propagated to other unit cells of the full layout design having the same classification. This copying approach eliminates the need to perform identical verification computations on every unit cell, reducing memory requirements and processing time while ensuring consistent verification across the entire layout.
2Manufacturing precision
If design verification is performed on the entire layout, then manufacturing precision is improved, but memory requirements increase significantly
Solution Approach 1:
The layout is segmented into unit cells with designated points of interest, allowing memory to store properties and classifications for representative samples rather than all layout data simultaneously. This segmentation reduces the quantity of data that must be held in memory during verification processes.
Solution Approach 2:
Verification results from unique patterns are copied and propagated to corresponding unit cells throughout the layout. This approach requires storing verification data only for representative unit cells rather than maintaining separate verification states for every layout element, significantly reducing memory requirements.
3Manufacturing precision
If resolution enhancement techniques are employed, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The system applies different classifications and verification approaches to different unit cells based on their specific geometric properties and points of interest. Rather than applying uniform complex processing to all layout elements, local quality principles allow simplified processing for regular patterns while maintaining enhanced verification where needed, balancing manufacturing precision with device complexity.
Data Source
AI summary
Systems and methods for layout analysis using unit cell properties. A method includes receiving a layout design and analyzing the layout design to identify unit cells in the layout design. The method includes designating points of interest each corresponding to a respective one of the unit cells and classifying the unit cells into a plurality of classifications using the points of interest and the corresponding properties. The method includes identifying unique patterns of the unit cells, and producing a reduced layout including the unique patterns of unit cells. The method includes performing layout processing on the reduced layout and propagating the process results from each of the unique patterns of unit cells in the reduced layout to other unit cells of the layout design having the same classification.