Semiconductor Layout Boundary Compensation for Pattern Transfer Precision
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Solution Overview
Problem
In semiconductor manufacturing, pattern differences due to diffraction and interference during photolithography lead to issues like pattern shift, bridge, and breakage at boundaries with varying pattern densities, causing connection failures between layers.
Innovation Solution
A layout design method that adjusts the pitch and line width of polygons near boundaries by increasing them gradually in arithmetic or geometric progression to maintain connections between layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the pattern size is reduced to increase integration density, then the manufacturing precision deteriorates due to optical diffraction and interference effects
Solution Approach 1:
The patent applies preliminary action by pre-adjusting the pitch of polygons in the dense pattern area before photolithography. Specifically, the pitch of N polygons closest to the boundary is increased in advance according to a predetermined adjustment magnitude, which compensates for the expected pattern shrinkage during exposure. This preliminary adjustment ensures that after photolithography, the pattern dimensions and positions match the design requirements, thereby resolving the contradiction between reduced pattern size and manufacturing precision.
Solution Approach 2:
The patent employs parameter changes by modifying the pitch parameter of polygons in the dense pattern area. The adjustment magnitude is determined based on the distance from the boundary and the pattern density, with the pitch being increased by a calculated amount. This parameter modification compensates for optical diffraction and interference effects, allowing smaller pattern sizes to be manufactured with maintained precision, thus resolving the contradiction between integration density and pattern transfer precision.
2Manufacturing precision
If the pitch is increased to improve pattern resolution at boundaries, then the connection between layers may be affected
Solution Approach 1:
The patent applies local quality by differentiating the pitch adjustment strategy between different regions. Only N polygons closest to the boundary in the dense pattern area have their pitch increased, while other polygons maintain their original pitch. The adjustment magnitude varies locally based on the distance from the boundary and local pattern density. This localized adjustment improves pattern resolution at critical boundary areas without unnecessarily altering connections in other regions, thus resolving the contradiction between pattern resolution and layer connection reliability.
Solution Approach 2:
The patent applies preliminary anti-action by pre-compensating for potential connection issues through controlled pitch adjustment. The adjustment magnitude is carefully calculated to be within a range that improves pattern resolution while maintaining sufficient overlap and connection with upper and lower layers. This preliminary compensation prevents connection failures before they occur, resolving the contradiction between improving pattern resolution and maintaining layer connection reliability.
3Manufacturing precision
If the pitch is uniformly increased across all polygons, then the pattern resolution improves, but the manufacturing complexity increases
Solution Approach 1:
The patent applies local quality by restricting pitch adjustment to only N polygons closest to the boundary in the dense pattern area, rather than uniformly adjusting all polygons. This localized approach focuses computational resources on critical regions where pattern resolution is most needed, reducing the overall complexity of the layout adjustment process while maintaining manufacturing precision where it matters most.
Solution Approach 2:
The patent applies segmentation by dividing the dense pattern area into multiple regions based on distance from the boundary. The N polygons closest to the boundary are identified and adjusted, while other polygons are left unchanged. This segmentation strategy simplifies the adjustment process by focusing only on critical boundary regions, thereby improving pattern resolution without proportionally increasing manufacturing complexity across the entire layout.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves pattern resolution and prevents connection failures by aligning patterns closer to their original positions, reducing abnormal phenomena and maintaining electrical connections.
Implementation Method 1
Due to the characteristics of light itself, such as diffraction, interference, and other semiconductor process effects
Implementation Method 2
Due to the characteristics of light itself, such as diffraction, interference, and other semiconductor process effects
Data Source
AI summary
A layout design method including the following steps is provided. A dense pattern area, a loose pattern area, and a boundary of a layout layer are identified. The loose pattern area is adjacent to the dense pattern area. The boundary is located between the dense pattern area and the loose pattern area. The dense pattern area comprises a plurality of polygons, and the loose pattern area comprises at least one polygon. A step of increasing a pitch and a line width is performed on N polygons of the plurality of polygons of the dense pattern area closest to the boundary, wherein the N is an integer. The step of increasing the pitch and the line width is limited to not affecting a first connection between the layout layer and a lower layer, nor a second connection between the layout layer and an upper layer.