Double Patterning Layout Checking via Graph-Based Conflict Detection
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Solution Overview
Problem
The existing photolithography techniques face challenges in maintaining feature density and resolution as pattern sizes approach the limit of the photolithographic process, leading to distortion and deviation in geometric layouts during the fabrication of integrated circuits, particularly with advanced double patterning technologies.
Innovation Solution
A layout checking method that analyzes layout segments on an integrated circuit to identify first-type and second-type conflicted edges, determines potential conflicted edges, and checks for odd-vertex loops, ensuring compliance with advanced double patterning rules by grouping layout segments into sub-groups and assigning them to different masks, thereby preventing design rule violations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If double patterning is used to enhance feature density, then the number of features is doubled, but non-linear imaging effects cause resolution blurring and geometric distortion
Solution Approach 1:
The patent applies preliminary action by performing layout decomposition and conflict detection before the actual photolithography process. The system identifies and resolves geometric conflicts and odd-vertex loops in advance, ensuring that the layout is optimized for double patterning before manufacturing begins. This prevents resolution blurring and geometric distortion by pre-validating the layout against double patterning rules.
Solution Approach 2:
The patent segments the layout into different components for analysis: layout segments are decomposed into graph representations with vertices and edges, and further segmented into conflict-free subgraphs. This segmentation allows the system to handle complex geometric relationships by breaking them down into manageable units that can be individually validated and optimized for double patterning.
2Manufacturing precision
If layout checking is performed to ensure double patterning compliance, then manufacturing precision is improved, but processing time increases due to complex analysis
Solution Approach 1:
The patent replaces traditional mechanical/layout-based checking methods with a graph-theoretic approach. By converting layout segments into graph representations and using mathematical algorithms to detect conflicts and odd-vertex loops, the system achieves faster and more automated compliance verification. This substitution of checking methodology reduces processing time while maintaining high precision.
Solution Approach 2:
The layout checking system performs self-service by automatically detecting and reporting conflicts without requiring manual intervention. The graph-based algorithm autonomously identifies odd-vertex loops and conflict edges, and the system provides self-contained validation results that indicate whether the layout complies with double patterning rules, eliminating the need for time-consuming manual review.
3Manufacturing precision
If multiple spacing criteria are enforced for advanced double patterning, then manufacturing precision is improved, but device complexity increases due to multiple conflict types
Solution Approach 1:
The patent applies universality by creating a unified graph-based framework that handles multiple spacing criteria and conflict types through a single mathematical model. The same graph representation and algorithmic approach are used to detect first-type conflicts, second-type conflicts, and odd-vertex loops, regardless of the specific spacing rule being violated. This universal method simplifies the overall system complexity while maintaining the ability to enforce multiple spacing criteria.
Solution Approach 2:
The patent uses parameter changes by representing different spacing criteria as numerical parameters in the graph model. By encoding spacing requirements as edge weights or vertex properties in the graph structure, the system can dynamically adjust and enforce multiple spacing rules without changing the fundamental checking algorithm. This parameter-based approach manages complexity by keeping the checking logic consistent while allowing flexible enforcement of different spacing standards.
Data Source
AI summary
In some embodiments, in a method performed by at least one processor, spaces among a plurality of layout segments is analyzed by the at least one processor to determine at least one first-type conflicted edge according to a first predetermined length. Spaces among the plurality of layout segments is analyzed by the at least one processor to determine a plurality of potential conflicted edges according to a second predetermined length different from the first predetermined length. At least one second-type conflicted edge is determined by the at least one processor according to the plurality of potential conflicted edges. If at least one odd-vertex loop is formed in the plurality of layout segments is checked by the at least one processor according to the at least one first-type conflicted edge and the at least one second-type conflicted edge to determine if a violation occurs in the plurality of layout segments.