Semiconductor Layout Correction for Multiple Patterning Computation
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Solution Overview
Problem
As semiconductor devices become highly integrated and nano-scale manufacturing technologies are applied, the number of patterns in semiconductor layouts increases significantly, leading to increased computation requirements for revising or changing layouts to compensate for process errors.
Innovation Solution
A method and computing device that utilize machine learning-based process proximity correction (PPC) and optical proximity correction (OPC) to generate improved semiconductor layouts, reducing computation complexity and enhancing resolution through multiple patterning processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional layout revision methods are used to compensate for process errors, then manufacturing precision is improved, but the amount of computation increases sharply
Solution Approach 1:
The patent segments the layout revision process into two distinct correction stages: optical proximity correction (OPC) that addresses optical diffraction effects, and process proximity correction (PPC) that addresses etching process variations. This segmentation allows each correction method to focus on specific error sources, improving overall manufacturing precision while managing computation complexity through specialized algorithms for each stage
Solution Approach 2:
The patent applies preliminary corrections to the layout design before manufacturing by pre-calculating and applying OPC and PPC adjustments. This preliminary action compensates for anticipated process errors and optical effects in advance, ensuring that the final manufactured device achieves the desired precision without requiring complex real-time computation during manufacturing
2Productivity
If the number of patterns in semiconductor layout increases, then device integration is improved, but the amount of computation for layout revision increases
Solution Approach 1:
The patent segments pattern correction by dividing patterns into first-type patterns (subject to first patterning process) and second-type patterns (subject to second patterning process). This segmentation enables independent optimization and computation for each pattern type, allowing high device integration while managing computation through specialized correction algorithms applied to each segment rather than treating all patterns uniformly
Solution Approach 2:
The patent changes the approach to handling pattern data by representing patterns as images and using machine learning models that process visual features. This parameter transformation from traditional geometric representations to image-based representations enables more efficient computation for highly integrated layouts with numerous patterns
Data Source
AI summary
A method for manufacturing a semiconductor device, includes receiving a first layout including patterns for the manufacturing of the semiconductor device, generating a second layout by performing machine learning-based process proximity correction (PPC) based on features of the patterns of the first layout, generating a third layout by performing optical proximity correction (OPC) on the second layout, and performing a multiple patterning process based on the third layout. The multiple patterning process includes patterning first-type patterns, and patterning second-type patterns. The machine learning-based process proximity correction is performed based on features of the first-type patterns and features of the second-type patterns.