Semiconductor Layout Decomposition for Density Uniformity
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Solution Overview
Problem
In semiconductor device manufacturing, the difference in pattern densities between decomposed patterns affects critical dimension uniformity and increases the loading effect during mask manufacturing and etching processes, particularly when using multiple patterning technologies like DPT, TPT, and QPT.
Innovation Solution
A method is introduced that involves determining complex polygons in the layout, inserting stitches and separators based on intersections and distances between polygons, and performing pattern dividing operations to generate decomposed patterns, which reduces pattern density differences and improves critical dimension uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a layout is decomposed into multiple patterns using DPT, TPT, or QPT processes, then the pattern density difference between decomposed patterns increases, but this leads to degraded critical dimension uniformity and increased loading effect during mask manufacturing and etching processes
Solution Approach 1:
The patent applies segmentation by dividing complex polygons into multiple sub-regions through stitching. The layout decomposition process segments polygons based on their density characteristics, creating separate pattern groups that can be processed independently. This segmentation allows for better control of pattern density distribution across different decomposed patterns, thereby improving critical dimension uniformity while managing the complexity of multi-pattern decomposition
Solution Approach 2:
The patent implements local quality by assigning different processing characteristics to different regions of the layout. Specifically, it calculates and compares pattern densities of individual polygons, and applies different stitching strategies to polygons with high density differences versus those with similar densities. This localized approach ensures that each region is decomposed according to its specific density characteristics, optimizing critical dimension uniformity locally across the entire layout
2Productivity
If pattern density differences between decomposed patterns are large, then the loading effect during mask manufacturing and etching processes increases, but this deteriorates process efficiency and manufacturing precision
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the decomposition strategy based on pattern density parameters. It calculates the pattern density of each polygon and uses these density values as key parameters to determine stitching locations and pattern grouping. By changing the decomposition parameters according to actual density measurements, the process optimizes the balance between productivity and minimizing loading effects, ensuring that no single decomposed pattern has excessively high or low density that would cause loading issues
Data Source
AI summary
In a method of decomposing a layout of a semiconductor device, a polygon, which includes a plurality of intersections at each of which at least two lines are crossed, among polygons included in the layout of the semiconductor device may be determined as a complex polygon. A first stitch may be inserted between the plurality of intersections on the complex polygon. A plurality of decomposed patterns may be generated by performing a pattern dividing operation on the layout.