Layout Decomposition via Graph Segmentation for Multi-Patterning
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Solution Overview
Problem
Current multi-patterning technologies for semiconductor manufacturing are inefficient in processing layout decomposition, particularly for semiconductor devices with dimensions of 20 mm or less, due to the complexity and time required for graph coloring operations.
Innovation Solution
A layout decomposition method and system that builds a graph from a layout design, identifies nodes with high degrees, splits the graph into subgraphs, and performs multi-patterning technology (MPT) decomposition in parallel to reduce the number of coloring cases, thereby accelerating the MPT decomposition process and mask creation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional graph coloring methods are used for MPT decomposition, then manufacturing precision can be maintained, but processing time and computational complexity increase significantly
Solution Approach 1:
The patent divides the layout design into multiple decomposition regions based on geometric features (convex/concave characteristics, area ratios, and adjacency relationships). Each region is processed independently through separate graph coloring operations, transforming one large complex computation into multiple smaller parallel computations. This segmentation maintains decomposition accuracy while significantly reducing processing time and computational complexity.
2Manufacturing precision
If the entire layout is processed as a single graph, then decomposition accuracy is maintained, but device complexity and processing difficulty increase
Solution Approach 1:
The layout is segmented into multiple decomposition regions using geometric criteria (convex/concave features, area ratios, adjacency). Each region generates a separate subgraph with fewer nodes and edges, reducing the complexity of graph coloring operations. The segmentation strategy ensures that each subgraph can be processed independently with lower computational requirements while maintaining overall decomposition accuracy.
Solution Approach 2:
The patent introduces a spatial dimension for graph partitioning by creating decomposition regions based on geometric characteristics and spatial relationships. This dimensional approach to partitioning transforms the problem from a single complex graph into multiple spatially-distributed subgraphs, making the computational problem more manageable while preserving the integrity of the overall decomposition.
3Productivity
If graph decomposition is performed without regional segmentation, then processing simplicity is maintained, but productivity and processing speed decrease
Solution Approach 1:
The method segments the layout into decomposition regions based on geometric features and processes each region independently. This segmentation enables parallel processing of multiple regions, significantly improving processing speed and productivity. The additional complexity of region identification is offset by the efficiency gains from parallel computation and reduced graph size.
Solution Approach 2:
The patent performs preliminary actions by identifying and marking decomposition regions before executing graph coloring operations. Regions are pre-classified based on geometric characteristics (convex/concave features, area ratios, adjacency relationships), and decomposition graphs are pre-constructed for each region. This preliminary organization enables more efficient subsequent processing and parallel execution.
Data Source
AI summary
A layout decomposition method is provided which may include building, a graph including a plurality of nodes and edges from a layout design including a plurality of polygons, wherein the nodes correspond to the polygons of the layout design and the edges identify two nodes disposed close to each other at a distance shorter than a minimum distance among the plurality of nodes, comparing degrees of the plurality of nodes with a reference value, selecting a target node, the degree of which exceeds the reference value, identifying a first and second subgraph based on the target node, performing multi-patterning technology decomposition on the first and second subgraph to acquire a first and second result, and creating first mask layout data corresponding to one portion of the layout design and second mask layout data corresponding to the other portion of the layout design by combining the first and second result.