Semiconductor Layout Decomposition for Odd-Numbered Feature Formation
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Solution Overview
Problem
Conventional photolithography techniques face limitations in forming reliable features with fine pitches due to wavelength constraints, leading to decreased yield and increased costs, and the 'pitch doubling' technique struggles with forming odd-numbered features effectively.
Innovation Solution
A layout decomposition method involving a logic processor that identifies dense and odd-numbered feature areas, generating masks to form even-numbered features using spacers, and then selectively removing or blocking odd-numbered features to create groups of odd-numbered features, enabling successful pattern transfer on semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If pitch doubling technique is used to extend photolithography capabilities beyond minimum pitch, then the number of features in a region is doubled, but the formation of odd-numbered features becomes problematic
Solution Approach 1:
The patent segments the feature formation process into distinct phases: first forming even-numbered features through pitch doubling, then separately addressing odd-numbered features through selective removal or additional patterning. This segmentation allows each type of feature to be handled with optimized processes, resolving the contradiction between achieving fine pitch and maintaining ease of manufacture for odd-numbered features.
Solution Approach 2:
The patent extracts and removes previously formed even-numbered features in specific areas where odd-numbered features are required. By taking out the unwanted even-numbered features through selective etching or removal processes, the patent enables the formation of odd-numbered features while maintaining the benefits of pitch doubling in other regions.
2Length of moving object
If conventional photolithography is used with reduced k1 values, then feature size is reduced, but yield decreases and cost increases
Solution Approach 1:
The patent employs periodic action through multi-step patterning processes, including pitch doubling and selective feature removal. Instead of attempting to form all features in a single exposure at reduced k1 values, the process is divided into periodic stages: first exposure for even-numbered features, then selective removal, and additional steps for odd-numbered features. This periodic approach maintains higher yield at each stage while achieving the overall feature size reduction.
Solution Approach 2:
The patent performs preliminary action by first forming the even-numbered features through pitch doubling before addressing the odd-numbered features. This preliminary formation of a subset of features allows subsequent selective removal and patterning to occur on a more manageable structure, improving overall process reliability compared to attempting to form all features simultaneously at reduced dimensions.
3Area of moving object
If feature size is reduced to meet smaller device requirements, then device integration is improved, but photolithography capability is exceeded
Solution Approach 1:
The patent applies dimensionality change by transitioning from direct planar patterning to a multi-dimensional approach involving vertical spacer formation and selective removal. Instead of relying solely on horizontal photolithography resolution, the process uses vertical dimension (spacer height) and selective etching dimensions to achieve fine pitch features that exceed conventional photolithography limits.
Solution Approach 2:
The patent introduces intermediary structures (spacers and placeholder features) that mediate between the photolithography process and the final fine-pitch features. The spacers act as intermediaries that transfer the pattern from the photolithography step to the final feature structure, enabling pitch multiplication and overcoming the direct resolution limits of photolithography.
Data Source
AI summary
A layout decomposition method and a method for manufacturing a semiconductor device applying the same are provided. According to the layout decomposition method, a design layout is received by the logic processor of a computing system. A design rule for layout decomposition is then identified by the logic processor, including identifying dense areas (areas with densely distributed features) on a substrate, and identifying areas with odd-numbered features on the substrate. Next, a first mask with a first pattern and a second mask with a second pattern are generated corresponding to results of design rule identification by the computing system for fabricating patterns of features in at least two of the areas with odd-numbered features in one of the dense areas.