Layout Decomposition Using Reference Pattern Assignment
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Solution Overview
Problem
Current layout decomposition processes in semiconductor fabrication are computationally resource-demanding and time-consuming, and they often result in inconsistent performance and yield rates due to the complexity of assigning layout patterns to multiple masks in double patterning technology.
Innovation Solution
A method that modifies the layout decomposition process by referencing a previous pattern-assigning result to reduce the number of layout patterns to be processed, minimizing differences between current and reference layout designs, and assigning patterns to masks in a way that maintains a minimum threshold distance between them, thereby reducing computational resources and processing time while ensuring consistent performance and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a full layout decomposition process is performed on the current layout design, then the pattern assignment is complete and accurate, but the computational resources and processing time are excessive
Solution Approach 1:
The patent performs layout decomposition on a reference layout design beforehand to obtain a reference pattern-assigning result. When processing the current layout design, it leverages this pre-computed reference result to identify only the modified layout patterns that require re-decomposition, rather than processing the entire layout from scratch. This preliminary action significantly reduces computational resources and processing time while maintaining pattern assignment accuracy.
2Productivity
If the layout decomposition process is simplified to reduce processing time, then computational resources are reduced, but the performance consistency and yield rates become inconsistent
Solution Approach 1:
The patent applies different processing strategies to different portions of the layout based on their modification status. Modified layout patterns are subjected to full decomposition analysis to ensure accuracy, while unmodified patterns leverage the reference result. This local quality approach ensures that critical modified regions receive adequate processing attention for consistency, while non-critical regions benefit from simplified processing, achieving both speed and reliability.
Solution Approach 2:
The patent uses the reference pattern-assigning result as feedback to guide the decomposition process for the current layout. By comparing the current layout with the reference layout and utilizing the reference decomposition result, the system can identify patterns that require re-decomposition and apply appropriate processing. This feedback mechanism ensures manufacturing performance consistency while reducing overall processing requirements.
3Manufacturing precision
If all layout patterns are processed independently without referencing previous results, then each pattern assignment is accurate, but the overall process is computationally resource-demanding
Solution Approach 1:
The patent merges the decomposition results of the reference layout with the current layout by identifying modified patterns and integrating their decomposition results with the reference result. This merging approach avoids redundant computation on unmodified patterns while maintaining accuracy for modified patterns, significantly reducing computational resource consumption compared to processing all patterns independently.
Data Source
AI summary
A method of assigning layout patterns includes identifying a first set of layout patterns of a current layout design that is new or has been modified in comparison with a reference layout design. A second set of layout patterns of the current layout design is identified. A member of the second set of layout patterns that is not a member of the first set of layout patterns has a distance, less than a predetermined threshold distance, to at least another member of the second set of layout patterns. A third set of layout patterns is not modified in comparison with the reference layout design. The third set of layout patterns is assigned to a plurality of masks according to the reference pattern-assigning result.