Semiconductor Layout Design Support for Density Error Correction
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Solution Overview
Problem
The existing layout design methods for semiconductor integrated circuits face inefficiencies in generating dummy patterns to satisfy physical design rules, particularly in maintaining uniform density, which can lead to manufacturing defects and increased design time due to repeated redesigns in hierarchical design methods.
Innovation Solution
A design support apparatus that stores layout data and pattern data, allowing it to specify and replace dummy patterns in areas with density errors, using pre-prepared dummy patterns of different shapes to adjust circuit densities and satisfy design constraints, thereby reducing redesigns and design time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dummy patterns are generated at a time for the entire design target circuit, then density constraints are satisfied, but design time increases significantly
Solution Approach 1:
The patent divides the design target circuit into multiple hierarchical levels (e.g., top-level circuit and component circuits). Dummy patterns are generated separately for each level rather than for the entire circuit at once. This segmentation allows density constraints to be satisfied at each hierarchical level independently, reducing the overall computational burden and design time while maintaining manufacturing precision.
Solution Approach 2:
The patent performs preliminary generation of dummy patterns at lower hierarchical levels before proceeding to higher levels. By preparing dummy patterns for component circuits first, the system establishes a foundation that simplifies subsequent density adjustments at the top level, avoiding the need for iterative redesign and reducing total design time.
2Manufacturing precision
If dummy patterns are generated using bottom-up hierarchical design method, then lower level density errors are resolved, but upper level density errors may still occur requiring redesign
Solution Approach 1:
The patent implements a feedback mechanism where density constraints are checked at each hierarchical level, and dummy patterns are adjusted based on the results. When upper level density errors are detected, the system provides feedback to modify dummy patterns at lower levels or add dummy patterns at the upper level, ensuring density constraints are satisfied throughout the hierarchy without requiring complete redesign.
Solution Approach 2:
The patent changes the parameters of dummy patterns (such as shape, size, or density) at different hierarchical levels to satisfy density constraints. By adjusting dummy pattern parameters at the upper level rather than redrawing entire lower-level circuits, the system maintains manufacturing precision while improving design efficiency.
3Adaptability or versatility
If multiple dummy patterns with different shapes are prepared for each component circuit, then density adjustment flexibility increases, but data storage requirements increase
Solution Approach 1:
The patent applies different dummy pattern shapes and densities to specific component circuits based on their local density requirements. Instead of using a single dummy pattern type for all circuits, the system selects appropriate dummy patterns locally for each component circuit, maximizing density adjustment flexibility while storing only the necessary pattern data.
Data Source
AI summary
A design support apparatus includes a storage that stores first layout data and pattern data, the first layout data indicating a circuit pattern of a design target circuit, the circuit pattern including circuit patterns, dummy patterns of the component circuits, and a wiring pattern, the component circuits being included in the design target circuit, the pattern data indicating a second dummy pattern, the second dummy pattern having a shape different from a shape of a first dummy pattern, the first dummy pattern being included in the first layout data, and a processor coupled to the storage, configured to specifies a component circuit, the specified component circuit being included in an area in the arrangement area, extracts pattern data indicating a dummy pattern, generates second layout data, the second layout data indicating a circuit pattern, and outputs the second layout data.