Layout Dependent Statistical Leakage Analysis for FinFET SoC
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Solution Overview
Problem
Accurate prediction of silicon leakage in modern system on a chip (SoC) designs is challenging due to the inability to model layout dependent effects (LDE) and Silicon-to-SPICE (S2S) factors for various digital domains, particularly in advanced FinFET processes.
Innovation Solution
A layout dependent statistical leakage analyzing method and system that utilizes pre-silicon data to determine pre-silicon leakage values, abutment possibilities, scaling factors, and layout dependent effects between cell groups, generating an estimated silicon leakage based on these factors, using a trained neural network model to improve prediction accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional leakage modeling methods are used, then the design process is simple, but the prediction accuracy of silicon leakage is poor
Solution Approach 1:
The chip is divided into multiple digital domains, each containing standard cells with specific threshold voltages. The leakage analysis is segmented by cell group types (i-th cell group, j-th cell group) and their spatial relationships (abutment relationships), allowing precise modeling of leakage sources while managing complexity through structured decomposition
Solution Approach 2:
The patent introduces a two-dimensional LDE factor that considers both the i-th cell group and j-th cell group dimensions, capturing layout-dependent effects in multiple spatial dimensions. This dimensional expansion enables accurate prediction of silicon leakage by accounting for physical layout displacements and abutment relationships between different cell groups
2Measurement precision
If layout dependent effects and S2S factors are not modeled, then the analyzing system is simple, but accurate prediction of silicon leakage remains challenging
Solution Approach 1:
The patent pre-calculates and stores LDE factors and S2S scaling factors for different cell group combinations before actual leakage analysis. These pre-computed factors (i-th LDE factor, j-th LDE factor, i-th S2S scaling factor) are saved in lookup tables, enabling fast and accurate leakage prediction without complex real-time calculations
Solution Approach 2:
The patent models leakage by changing key parameters including threshold voltages of standard cells, physical layout displacements between cell groups, abutment possibilities, and S2S scaling factors. These parameter variations capture the essential physics of leakage while maintaining computational efficiency through parameterized models
Data Source
AI summary
A layout dependent statistical leakage analyzing method includes providing pre-silicon data, acquiring an i-th pre-silicon leakage value of an i-th cell group according to the pre-silicon data, acquiring an (i,j)-th abutment possibility of a j-th cell group abutted on the i-th cell group according to physical information extracted from the pre-silicon data, acquiring an i-th scaling factor for a Silicon-to-SPICE (S2S) of the i-th cell group according to the pre-silicon data, acquiring an (i,j)-th layout dependent effect (LDE) factor between the i-th cell group and the j-th cell group according to the pre-silicon data and post-silicon data, and generating an estimated silicon leakage of a block according to N pre-silicon leakage values, N2 abutment possibilities, N scaling factors, and N2 LDE factors.