Semiconductor Layout Design Tool Pattern Extraction
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Solution Overview
Problem
Current semiconductor layout design tools face inefficiencies in modifying regions with the same pattern groups, leading to high computational requirements and prolonged processing times.
Innovation Solution
A layout design tool with a modifying module that designates modification regions with the same pattern groups, extracts a pattern group, generates a temporary pattern layer, and places it on transform regions on a background layer, reducing computational load by performing the extraction operation only once.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional layout modification methods are used to modify regions with the same pattern groups, then the layout can be modified, but computational requirements increase and processing time prolongs
Solution Approach 1:
The patent merges multiple pattern groups with the same shape into a single representative pattern. Instead of processing each pattern group individually, the system extracts one representative pattern and applies it to all modification regions, combining multiple processing operations into one efficient operation.
Solution Approach 2:
The extracted representative pattern serves multiple functions simultaneously - it acts as the modification template for all modification regions containing the same pattern group. This universal pattern can be applied across different locations and contexts within the layout, eliminating redundant processing.
2Manufacturing precision
If traditional layout modification methods process each pattern group separately, then modification accuracy is maintained, but processing time increases
Solution Approach 1:
The patent extracts a single representative pattern from among multiple pattern groups with the same shape. This extracted pattern contains all the necessary geometric and structural information needed for accurate modification, while eliminating the time-consuming process of separately processing each individual pattern group.
Solution Approach 2:
The system performs preliminary extraction of the representative pattern before applying modifications. By preparing this universal pattern template in advance, the system avoids repeated extraction operations during the modification process, significantly reducing overall processing time while maintaining accuracy.
Data Source
AI summary
A layout design tool for generating a layout graphic based on a first input and a modification input includes a processing circuitry that generates a temporary layout in which a pattern is scripted based on the first input, and modifies the temporary layout based on the modification input to generate the layout graphic, and the processing circuitry designates a plurality of modification regions to be modified on the temporary layout based on the modification input and designates a plurality of transform regions on a background layer, the plurality of modification regions of the temporary layout, and the layout design tool generates a pattern layer by extracting the pattern group included in any one of the plurality of modification regions and generates the layout graphic by placing the pattern layer on the plurality of transform regions of the background layer.