Semiconductor Layout Dummy Pattern Conversion for Signal Delay
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Solution Overview
Problem
Existing semiconductor manufacturing processes face challenges in reducing signal propagation delay due to high electrical resistance in layout diagrams, particularly after the dummy fill process, which affects the performance of integrated circuits.
Innovation Solution
The method involves converting adjacent dummy patterns into an electrically parallel configuration with routed patterns in the layout diagram, reducing resistance by adding jumper patterns and via patterns, thereby optimizing the layout to minimize signal propagation delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If dummy fill process is performed to complete the layout diagram, then the layout diagram is fully populated with patterns, but electrical resistance increases and signal propagation delay worsens
Solution Approach 1:
The patent merges adjacent dummy patterns into electrically parallel configurations with routed patterns. By combining multiple parallel conductive paths, the equivalent resistance is reduced while maintaining the complete pattern coverage achieved through dummy fill. This resolves the contradiction by making the dummy patterns serve dual purposes: filling gaps and providing low-resistance parallel conduction paths.
Solution Approach 2:
The patent changes the electrical configuration parameter of dummy patterns from isolated single-path conductors to multi-path parallel configurations. By altering the topological arrangement and electrical connectivity parameters of dummy patterns, the system achieves both complete coverage and reduced resistance simultaneously.
2Loss of energy
If dummy patterns are converted to electrically parallel configuration with routed patterns, then electrical resistance is reduced, but layout diagram complexity increases
Solution Approach 1:
The dummy patterns, which were originally added solely for structural completion, are made to serve an additional electrical function by converting them into parallel conduction paths. This self-service approach reduces resistance without requiring separate dedicated low-resistance structures, thereby limiting the increase in overall layout complexity.
Solution Approach 2:
The dummy patterns are transformed from having a single function (filling gaps) to multiple functions (filling gaps and providing parallel conduction paths). This multi-functionality allows the same structural elements to address both layout completion and electrical performance requirements, minimizing the net increase in complexity.
3Loss of time
If adjacent dummy patterns are converted into electrically parallel configuration, then signal propagation delay is minimized, but manufacturing process complexity increases
Solution Approach 1:
The conversion of dummy patterns to electrically parallel configurations is performed during the layout diagram generation phase, before fabrication. By preparing the parallel configuration structure in advance through design-time optimization, the manufacturing process benefits from reduced signal propagation delay without adding complexity during actual fabrication, as the structure is already in place.
Data Source
AI summary
A method (of revising an initial layout diagram of a wire routing arrangement, the initial layout diagram and versions thereof being stored on a non-transitory computer-readable medium) includes identifying, in a first conductance layer of the initial layout diagram, a routed pattern and a dummy pattern, each of which extends in a first direction and revising to form a revised layout diagram. The routed patterns are functional in a representation of a circuit and the dummy patterns are non-functional in the representation of the circuit. The revising includes connecting first ends of the corresponding routed and dummy patterns and connecting second ends of the corresponding routed and dummy patterns.