Semiconductor Layout Edge Center Point Characterization
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Solution Overview
Problem
Existing physical verification analyses for semiconductor layout designs are processing and memory intensive due to the use of pixel-based images, and they struggle with reconstructing characterized portions of the layout design reliably.
Innovation Solution
A computing system implementing a physical verification tool that identifies edges of geometric patterns around a point of interest in a semiconductor layout design, characterizes these edges based on center points, and generates geometrical feature vectors for reconstruction of the layout design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pixel-based images are used for physical verification analyses, then geometric shapes can be identified effectively, but processing and memory requirements become intensive
Solution Approach 1:
The layout design is divided into multiple tiles, and each tile is further segmented into edges with center points. This segmentation allows the system to process only relevant portions of the layout rather than entire pixel-based images, reducing processing and memory requirements while maintaining identification accuracy through systematic edge sampling.
Solution Approach 2:
The patent extracts only the essential geometric information (edge center points and their coordinates) from the layout design, discarding the unnecessary pixel data. This extraction approach retains the critical features needed for verification while eliminating the computational burden of processing complete pixel-based images.
2Adaptability or versatility
If numerical characterization of geometric shapes is used, then granular comparisons of pattern types are enabled, but reconstruction of the characterized portion becomes unreliable
Solution Approach 1:
The patent creates a faithful copy of the geometric pattern by systematically recording the coordinates of edge center points and reconstructing the pattern from these points. This copying method preserves the exact geometric information needed for reliable reconstruction while enabling granular pattern comparisons through the structured numerical representation of edge characteristics.
Data Source
AI summary
A computing system implementing a physical verification tool can identify edges of a geometric pattern located within a search area surrounding a point of interest in a semiconductor layout design, characterize the edges of the geometric pattern based on locations of center points of the edges from the point of interest within the search area, and generate geometrical feature vectors for the point of interest in the semiconductor layout design based on the characterization of the edges of the geometric pattern. The computing system can reconstruct the semiconductor layout design corresponding to the search area surrounding the point of interest using the geometrical feature vectors for the point of interest in the semiconductor layout design.