Semiconductor Layout Insulating Structures Stress Relief

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Solution Overview

Problem

The challenge in semiconductor device fabrication is to create a layout design that enhances the reliability of miniaturized devices by ensuring proper insulation between transistors and preventing excessive stress that can alter transistor properties.

Innovation Solution

A layout design system that includes insulating structures extending in specific directions, spaced apart to prevent excessive stress and ensure proper insulation, is implemented. This system uses a processor to generate filler designs with insulating structures arranged between standard cell designs, preventing insulating structures from forming in line and reducing stress on transistors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If insulating structures are placed adjacent to each other in standard cell designs, then insulation between transistors is improved, but stress on transistors increases causing property changes

Engineering Contradiction:

Improveinsulation between transistorsVSAvoidstress on transistors

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A filler cell is introduced as an intermediary element between standard cell designs. The filler cell contains insulating structures that are spaced apart from each other, creating a buffer zone that maintains insulation between adjacent standard cells while reducing the stress concentration that would otherwise affect transistors in neighboring cells.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The insulating structures in the filler cell are arranged in a spaced-apart configuration rather than being continuously adjacent, effectively creating a dimensional separation pattern. This spacing arrangement allows the insulating function to be maintained while the stress propagation is disrupted through the gaps between structures.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Volume of moving object

If miniaturization of semiconductor devices is pursued, then device compactness is improved, but reliability and insulation properties deteriorate

Engineering Contradiction:

Improvedevice sizeVSAvoidinsulation and transistor property stability

Core Design Contradiction:

Volume of moving objectVSReliability

Solution Approach 1:

The semiconductor device layout is segmented into standard cell designs and filler cells with alternating patterns. This segmentation allows the compact standard cells to be interspersed with filler cells that provide stress relief and insulation, maintaining reliability while enabling overall device miniaturization through efficient space utilization.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS10540471B2Layout design system and semiconductor device fabricated using the same

Publication Date: 2020.01.21 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor device is provided. A semiconductor device includes a filler cell including first and second insulating structures, the first and second insulating structures extending in a first direction, the filler cell being defined by first cell boundaries; and a neighboring cell including a third insulating structure, the third insulating structure extending in the first direction, the neighboring cell being adjacent to the filler cell in the first direction and defined by second cell boundaries, wherein the first and second insulating structures are spaced apart from one another in a second direction, is the second direction being perpendicular to the first direction.