Layout Design Overlay View for DRC Violation Resolution
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Solution Overview
Problem
Designing integrated circuits is hindered by the time-consuming process of identifying and correcting design rule violations across multiple instance circuit cells, as changes to one instance can introduce errors in others, requiring manual review and modification of each cell individually.
Innovation Solution
A graphical user interface is provided with an overlap view that displays external circuit elements causing design rule errors for multiple instance circuit cells simultaneously, allowing designers to modify the master circuit cell and view resulting errors in a single location, reducing the need for individual cell reviews.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If designers manually review and modify each instance circuit cell individually to fix DRC violations, then design accuracy is maintained, but design time and productivity are significantly reduced
Solution Approach 1:
The patent combines multiple instance circuit cell views into a single overlay display, allowing designers to see all instances and their DRC violations simultaneously. This merging of views enables batch identification and correction of violations across multiple instances without manually reviewing each cell separately, thus maintaining design accuracy while significantly improving productivity.
Solution Approach 2:
The overlay view acts as an intermediary between the master circuit cell and individual instance circuit cells. It displays external circuit elements that cause DRC violations in relation to multiple instances simultaneously, serving as a mediator that consolidates information from multiple sources into a single actionable view for the designer.
2Ease of manufacture
If designers modify the master circuit cell to fix DRC violations, then corrections are propagated to all instances, but tracking which instances have errors becomes complex
Solution Approach 1:
The overlay view uses visual indicators such as color coding to highlight external circuit elements that cause DRC violations. Different visual states indicate whether violations exist in the master cell, individual instances, or both, providing an intuitive tracking system that reduces the complexity of monitoring which instances have errors without requiring complex data structures or manual tracking.
3Measurement precision
If designers view each instance circuit cell separately to identify DRC violations, then detailed analysis is possible, but the process becomes time-consuming and inefficient
Solution Approach 1:
The overlay view segments and displays information about DRC violations in a structured manner, showing external circuit elements and their relationships to multiple instances simultaneously. This segmentation allows designers to quickly identify which instances have violations and what specific elements are causing problems, maintaining detailed analysis capability while reducing the time required to review all instances compared to viewing them separately.
Data Source
AI summary
The present embodiments relate to providing an overlap view of external and internal components of all instance circuit cells related to a master circuit cell in a same layout view. A layout of a circuit having a plurality of instance circuit cells of a master circuit cell is provided. Further, a graphical user interface including a user selectable option for an overlay view is provided. In addition, responsive to the selection of the overlay view, the plurality of instance circuit cells of the master circuit cell is determined. In addition, a plurality of sets of circuit elements, each set of circuit elements including external circuit elements that overlap with a corresponding instance circuit cell of the plurality of instance circuit cells is determined. Further, the plurality of sets of circuit elements overlaid on the master circuit cell is displayed on the layout view.